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DP8483N
TTL to 100k ECL Level Translator with Latch
TL/F/5864
DP8483
TTL
100k
ECL
Level
Translator
with
Latch
April 1990
DP8483 TTL to 100k ECL Level Translator with Latch
General Description
This circuit translatesTTL input levelsto ECL output levels
and provides afall-throughlatch.The outputsare gatedwith providingfor wire ORingof outputs.The strobe andchip
select inputs operateat ECL levels.
Features 16-pinDIPor S.O. ECL control inputsCS providedfor wire ORingof outputbus 100k ECLI/O compatible3.0ns typical propagation delay
Logic and Connection Diagram
Dual-In-Line Package
TL/F/5864–1
Top View
Truth Table STR CS L H L H HH X L
Hehighlevel (most positive)
Lelow level(most negative)
Xedon’tcare
Order NumberDP8483J,
DP8483Mor DP8483N
SeeNS Package NumberJ16A, M16Bor N16A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
