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DS90C383BMT ,+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHzFeaturesn No special start-up sequence required betweenThe DS90C383B transmitter converts 28 bits o ..
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DP8392CN-2
DP8392 Coaxial Transceiver Interface
TL/F/7405
DP8392A/NS32492A
Coaxial
Transceiver
Interface
May 1988
DP8392A/NS32492A Coaxial Transceiver Interface
General Description
The DP8392A Coaxial Transceiver Interface (CTI)isa coax-
ial cable line driver/receiverfor Ethernet/Thin Ethernet
(Cheapernet) type local area networks.TheCTIis connect- betweenthe coaxial cableandthe Data Terminal Equip-
ment (DTE).In Ethernet applicationsthe transceiveris usu-
allymounted withina dedicated enclosureand isconnectedthe DTEviaa transceiver cable.In Cheapernet applica-
tions,theCTIis typically located withinthe DTE and con-
nectstothe DTE through isolation transformers only.The
CTI consistsofa Receiver, Transmitter, Collision Detector,
anda Jabber Timer. The Transmitter connects directlytoa ohm coaxial cable whereitis usedto drivethe coax
when transmitting. During transmission,a jabber timerisini-
tiatedto disabletheCTI transmitterinthe eventofa longer
than legal length data packet. Collision Detection circuitry
monitorsthe signalsonthe coaxto determinethe presence colliding packets and signalsthe DTEinthe eventofa
collision.
TheCTIispartofa three chipsetthat implementsthe com-
plete IEEE 802.3 compatible network node electronicsas
shown below. The othertwo chipsarethe DP8391 Serial
Network Interface (SNI)andthe DP8390 Network Interface
Controller (NIC).
The SNI providesthe Manchester encodingand decoding
functions; whereastheNIC handlesthe Media Access Pro-
tocol andthe buffer management tasks. Isolation between
theCTIandtheSNIisan IEEE 802.3 requirementthatcan easily satisfiedon signal lines usingasetof pulse trans-
formers that comeina standard DIP. However,the power
isolationfor the CTIis doneby DC-to-DC conversion
througha power transformer.
Features Compatible with EthernetII, IEEE 802.3 10Base5 and
10Base2 (Cheapernet) Integratesall transceiver electronics except signal&
power isolation Innovative design minimizes external component count Jabber timer function integratedon chip Externally selectable CD Heartbeat allows operation
with IEEE 802.3 compatible repeaters Precision circuitry implements receive mode collision
detection Squelch circuitryatall inputs rejects noise Designed for rigorous reliability requirements of
IEEE 802.3 Standard Outline 16-pin DIP usesa special leadframe
that significantly reducesthe operatingdie temperature
Tableof Contents
1.0 System Diagram
2.0 Block Diagram
3.0 Functional Description
3.1 Receiverand Squelch
3.2 Transmitterand Squelch
3.3 Collisionand Heartbeat
3.4 Jabber Timer
4.0 Connection Diagram
5.0 Pin Descriptions
6.0 Absolute Maximum Ratings
7.0 Electrical Characteristics
8.0 Switching Characteristics
9.0 Timingand Load Diagram
10.0 Physical Dimensions
1.0 System Diagram
TL/F/7405–1
IEEE802.3 CompatibleEthernet/CheapernetLocalArea Network ChipSet
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
