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DP83902AVLJ ,ST-NIC Serial Network Interface Controller for Twisted PairPIN DESCRIPTIONand efficient packet transmission and reception control by3.0
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DP83902AV-DP83902AVJG-DP83902AVLJ
ST-NIC Serial Network Interface Controller for Twisted Pair
TL/F/11157
DP83902A
ST-NIC
Serial
Network
Interface
Controller
for
Twisted
Pair
PRELIMINARY
November 1995
DP83902A ST-NICTM
Serial Network Interface Controller for Twisted Pair
General Description
The DP83902A Serial Network Interface Controllerfor
Twisted Pair (ST-NIC)isa microCMOS VLSI devicede-
signedfor easy implementationof CSMA/CD local areanet-
works. These include Ethernet (10BASE5), Thin Ethernet
(10BASE2) and Twisted-pair Ethernet (10BASE-T). The
overall ST-NIC solution providesthe Media Access Control
(MAC)and Encode-Decode (ENDEC) withanAUI interface,
and 10BASE-Ttransceiver functionsin accordancewiththe
IEEE 802.3 standards.
The DP83902A’s 10BASE-T transceiver fully complies with
the IEEE standard. This functional block incorporatesthe
receiver, transmitter, collision, heartbeat, loopback, jabber,
andlink integrity blocksas definedinthe standard. The
transceiver when combined with equalization resistors,
transmit/receive filters,and pulse transformers providesa
complete physical interface fromthe DP83902A’s ENDEC
moduleandthe twistedpair medium.
The integrated ENDEC module allows Manchester encod-
ing and decodingviaa differential transceiver and phase
lock loop decoderat10 Mbit/sec. Also includedare colli-
sion detect translator and diagnostic loopback capability.
The ENDEC module interfaces directlytothe transceiver
module,and also providesa fully IEEE compliantAUI(At-
tachment Unit Interface)for connectionto other media
transceivers. (Continued)
Features Single chip solutionfor IEEE 802.3, 10BASE-T Integrated controller, ENDEC,and transceiver FullAUI interfaceNo external precision components required3 levelsof loopback supported
Transceiver Module Integrates transceiver electronics, including: Transmitterand receiver Collision detect, heartbeatand jabber timer Link integritytest Link disableand polarity detection/correction Integrated smart receive squelch Reduced squelch levelfor extended distance cableop-
eration (100-pin QFP version)
ENDEC Module10 Mb/s Manchester encoding/decoding, plus clockre-
covery Transmitterhalforfull step mode Squelchon receiveand collision pairs Lock time5bits typical Decodes Manchester data withupto g18ns jitter
MAC/Controller Module 100% DP8390 software/hardware compatible Dual 16-bit DMA channels 16-byte internal FIFO Efficient buffer management implementation Independent systemand network clocks Supports physical, multicast and broadcast addressfil-
tering Network statistics storage
1.0 System Diagram
Stationor DTE
TL/F/11157–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
ST-NICTMisa trademark ofNationalSemiconductor Corporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
