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DP83865BVH
Gig PHYTER V 10/100/1000 Ethernet Physical Layer
65B
Gig P
® V
10
/10
0 E
rnet
ysi
cal
Lay
ADVANCED INFORMATIONSeptember 2002
General DescriptionThe DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor’s South
Portland, Maine facility.
The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Twisted Pair media via an external transformer. This device
interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII) or the
IEEE 802.3z Gigabit Media Independent Interface (GMII).
The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor-
mance ensures drop-in replacement of existing 10/100
Mb/s equipment with 10/100/1000 Mb/s networking infra-
structure.
ApplicationsThe DP83865 fits applications in: 10/100/1000 Mb/s capable node cards Switches with 10/100/1000 Mb/s capable ports High speed uplink ports (backbone)
System DiagramRJ-45
DP8386510/100/1000 Mb/s
ETHERNET PHYSICAL LAYER
25 MHz
crystal or oscillator
STATUS
LEDs
DP8382010/100/1000 Mb/s
ETHERNET MAC
MII
GMII
10BASE-T
100BASE-TX
1000BASE-T
Features Fully compliant with IEEE 10BASE-T, 100BASE-TX and
1000BASE-T specifications (802.3u, 802.3z, 802.3ab). Integrated PMD sublayer featuring adaptive equalization
and baseline wander compensation according to ANSI
X3.T12. 3.3 V or 2.5 V MAC interfaces: IEEE 802.3u MII IEEE 802.3z GMII User programmable GMII pin ordering. IEEE 802.3u Auto-Negotiation and Parallel Detection Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,
and 10 Mb/s full duplex and half duplex devices LED support for activity, full / half duplex, link1000,
link100 and link10 or user programmable (manual
on/off). Supports 25 MHz operation with crystal or oscillator. Requires only two power supplies, 1.8 V (core and ana-
log) and 2.5 V (analog and I/O). 3.3V is supported as an
alternative supply for I/O voltage. User programmable interrupt. Supports Auto-MDIX at 10, 100 and 1000 Mb/s. Supports JTAG (IEEE1149.1). Ultra low power consumption of one watt typical. Management port (MDC / MDIO). 128-pin PQFP package (14mm x 20mm). WOL support.
DP83865BVH Gig PHYTER®
V
10/100/1000 Ethernet Physical Layer
