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DP8344BV
Biphase Communications Processor-BCP
TL/F/9336
DP8344B
Biphase
Communications
ProcessorÐBCP
November 1991
DP8344B Biphase Communications ProcessorÐBCPÉ
General Description
The DP8344B BCPisa communications processorde-
signedto efficiently process IBMÉ 3270, 3299 and 5250
communications protocols.A general purpose8-bit protocol also supported.
The BCP integratesa20 MHz 8-bit Harvard architecture
RISC processor, andan intelligent, software-configurable
transceiveronthe samelow power microCMOS chip.The
transceiveris capableof operating without significant proc-
essor interaction, releasingprocessor powerfor other tasks.
Fastand flexible interrupt and subroutine capabilities with
on-chip stacks makethis power readily available.
The transceiveris mapped intothe processor’s register
space, communicating withthe processorviaan asynchro-
nous interface which enables both sectionsofthe chipto
run from different clock sources.The transmitterand receiv-runatthe same basic clock frequency althoughthere-
ceiver extractsa clock fromthe incoming data streamto
ensure timing accuracy.
The BCP isdesignedto stand aloneandis capable ofimple-
mentinga complete communications interface, usingthe
processor’s spare powerto controlthe complete system.
Alternatively,the BCPcanbe interfacedto another proces-
sorwithan on-chip interface controller arbitrating accessto
data memory. Accessto program memoryis also possible,
providingthe abilityto download BCP code. simpleline interface connectsthe BCPto thecommunica-
tions line.The receiver includesan on-chip analog compar-
ator, suitableforuseina transformer-coupled environment,
althougha TTL-level serial inputis alsoprovidedfor applica-
tions wherean external comparatoris preferred. typical systemis shown below. Both coaxand twinaxline
interfacesare shown,aswellasan exampleofthe (option-
al) remote processor interface.
Features
Transceiver Software configurablefor 3270, 3299, 5250and general
8-bit protocols Fully registered statusand control On-chip analogline receiver
Processor20 MHz clock(50ns T-states) Max. instruction cycle:200ns33 instruction types(50 total opcodes) ALUand barrel shifter 64kx8 data memory address range 64kx16 program memory address range
(note: typical system requires k2k program memory) Programmable wait states Soft-loadable program memory Interruptand subroutine capability Stand aloneor host operation Flexiblebus interface with on-chip arbitration logic
General Low power microCMOS;typ.ICCe25mAat20 MHz 84-pin plastic leaded chip carrier (PLCC) package
Block Diagram
Typical BCP System
TL/F/9336–51FIGURE1
BCPÉ andTRI-STATEÉare registeredtrademarksof National SemiconductorCorporation.
IBMÉ isaregistered trademarkof InternationalBusiness Machines Corporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
