DM93L28N ,Dual 8-Bit Shift RegisterFunctional DescriptionThe two 8-bit shift registers have a common clock input logic HIGH signal. Ea ..
DM93L38N ,8-Bit Multiple Port Registerapplications where the read without race problemsability to simultaneously read and write is desira ..
DM93S41N ,4-Bit Arithmetic Logic UnitGeneral DescriptionThe DM93S41 4-bit arithmetic logic units can perform allthe possible 16 logic op ..
DM93S62N ,9-Input Parity Checker/GeneratorGeneral DescriptionThe DM93S62 is a very high speed 9-input parity checker/generator for use in err ..
DM9601J ,Retriggerable One ShotFeaturesY lHigh speed operationÐinput repetition rate 10 MHzThese retriggerable one shots provide t ..
DM9602N ,Dual Retriggerable, Resettable One ShotsDM9602 Dual Retriggerable, Resettable One ShotsAugust 1986Revised February 2000DM9602Dual Retrigger ..
DS2740BU+ ,High-Precision Coulomb Counterapplications. Current is measured bidirectionally over a dynamic range of 15 bits (DS2740U) or 13 b ..
DS2740U ,High-Precision Coulomb CounterApplications Current Accumulation RegisterResolution 6.25Vhr (Both DS2740 andDS2740B) 0.3125mAh ..
DS2745 ,Low-Cost I²C Battery Monitorapplications. The DS2745 can be mounted on either the host side or 70A typical, 100A max pack sid ..
DS2745 ,Low-Cost I²C Battery MonitorBLOCK DIAGRAM 2 measurement takes place on-chip. A standard I C interface with software programmab ..
DS2745U+ ,Low-Cost I²C Battery MonitorAPPLICATIONS Cellular GPS PDAs Handheld Products Table 1. ORDERING INFORMATION PART MARKING PI ..
DS2745U+ ,Low-Cost I²C Battery MonitorFEATURES 16-Bit Bidirectional Current Measurement 1.56V LSB, ±51.2mV Dynamic Range 1 8 VDD S ..
DM93L28N
Dual 8-Bit Shift Register
DM93L28 Dual 8-Bit Shift Register March 1989 Revised August 1999 DM93L28 Dual 8-Bit Shift Register General Description Features The DM93L28 is a high speed serial storage element pro- � 2-input multiplexer provided at data input of each viding 16 bits of storage in the form of two 8-bit registers. register The multifunctional capability of this device is provided by � Gated clock input circuitry several features: 1) additional gating is provided at the � Both true and complementary outputs provided from last input to both shift registers so that the input is easily multi- bit of each register plexed between two sources; 2) the clock of each register � Asynchronous master reset common to both registers may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input. Ordering Code: Order Number Package Number Package Description DM93L28N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram V = Pin 16 GND = Pin 8 CC Pin Descriptions Pin Names Description S Data Select Input D0, D1 Data Inputs CP Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) MR Master Reset Input (Active LOW) Q7 Last Stage Output Q7 Complementary Output © 1999 DS010200
