DM87S184N ,55 ns, (2048 x 4) 8192-bit TTL PROMBlock Diagram
1 EIBZ-EIT ARRAY
" M x128
DECDDER MEMORY MATRIX
Pin Names -
AO-AIO Address;
..
DM87S185BJ ,35 ns, (2048 x 4) 8192-bit TTL PROMBlock Diagram
A9
"
A7 61_4
Mi usconan
A5
A4
8192-8" ARRAY
64 x123
MEMORY MATRIX
..
DM87S185J ,55 ns, (2048 x 4) 8192-bit TTL PROMBlock Diagram
A9
"
A7 61_4
Mi usconan
A5
A4
8192-8" ARRAY
64 x123
MEMORY MATRIX
..
DM87S185N ,55 ns, (2048 x 4) 8192-bit TTL PROMDM77S185/DM87S185
National
Semiconductor
DM77/87S185
(2048 x 4) 8192-Bit TTL PROM
DM87S185N ,55 ns, (2048 x 4) 8192-bit TTL PROMGeneral Description
This Schottky memory is organized in the popular 2048
words by 4 bits confi ..
DM87S281N ,(1024 x 8) 8192-BIT TTL PROMsFeatures
I Advanced titanium-tungsten (Ti-W) fuses
I Schottky-clamped for high speed
Address a ..
DS26LS31CMX ,Quad High Speed Differential Line Driversfeatures TRI-STATEn Complementary outputsoutputs and logically ANDed complementary outputs. Then Me ..
DS26LS31CN ,Quad High Speed Differential Line DriversFeaturesn Output skew—2.0 ns typicalThe DS26LS31 is a quad differential line driver designed fordig ..
DS26LS31MJ/883 ,Quad High Speed Differential Line Driversfeatures a power up/down protection circuit which keeps the output in a highimpedance state (TRI-ST ..
DS26LS31MW/883 ,Quad High Speed Differential Line DriversFEATURES SECTIONoProcessing Subgrp Description Temp ( C)MIL-STD-883, Method 5004 1 Static tests ..
DS26LS31MW/883 ,Quad High Speed Differential Line DriversDS26LS31C/DS26LS31M Quad High Speed Differential Line DriverJune 1998DS26LS31C/DS26LS31MQuad High S ..
DS26LS32 ,Quad Differential Line ReceiversLogic DiagramDS005255-1®TRI-STATE is a registered trademark of National Semiconductor Corporation. ..
DM87S184N
60 ns, (2048 x 4) 8192-bit TTL PROM
DM77S184/DM87S184
_ National
Semiconductor
DM77/87S184
(2048 x 4) 8192-Bit TTL PROM
General Description Features
This Schottky memory is organized in the popular 2048 II Advanced titanium-tungsten (Ti-W) fuses
words by 4 bits configuration. A memory enable input is pro- 1: Schottky-clamped for high speed
vided to control the output states. When the device is en- Address acCess--55 ns max
abled, the outputs represent the contents of the selected Enable access-N ns max
word. When disabled, the 4 outputs go to the "OFF" or high Enable recovery-25 ns max
impedance state. I: PNP inputs for reduced input loading
PROMs are shipped from the factory with lows in all loca- II All DC and AC parameters guaranteed over
tions. A high may be programmed into any selected location temperature
by following the programming instructions. I: Low voltage TRI-SAFETM programming
n Open-collector outputs
Block Diagram
A7 8192.iyT ARRAY
TiT 64x123
M Dscnusn MEMORY MATRIX
e Pln Names
AO-AIO Addresses
A10 G Output Enable
'll GND Ground
'li (20-O3 Outputs
Vcc Power Supply
ENABLE
BUFFER
TL/D/9717-1
Connection Diagrams
Dual-ln-Llne Package Plastlc Leaded Chip Carrier (PLCC)
15-1 V 1.1“ ff???
AS- 2 17 .-h7 3 2 1 20 19
M- 3 16 -A8 M-- 4 18 -h8
A3- 4 15 ~A9 AS- 5 17 -A9
AO-" 5 14 -00 M- 6 16 -'00
A1-6 13 --ol A1-7 15-NC
M--? 12 -02 h2-8 14 -01
AIO-B 11-03 9 10 11 12 13
tmo-ug IO-G 1 L'OFLL
TL/D/9717-2 TL/D/9717-3
Top View Top View
Order Number DM77l87S184J, Order Number DM87S184V, 184AV
184AJ or DM87S184N, 184AN See NS Package Number V20A
See NS Package Number J18A or N18A
Ordering Information
Commercial Temp Range ttt'C to + 70°C)
Parameter/Order Number Max Acces Time (ns)
DM87S184AN 45
DM87S184N 55 .. .
DM87S184AJ 45
DM87S184J 55
DM87S184AV 45
DM87S1 84V 55
Mllltary Temp Range ( - 55''C to + 125°C)
Parameter/Order Number Max Acces Time (n3)
DM77S1 840 70
DM77S1 84AJ 60
WLSZBWG/Vfl LSLLWG
DM77S184/DM87S184
Absolute Maximum Ratings (Note1)
Operating Conditions
If Mllltary/Aerospace speclfled devices are required, Min Max Units
please contact the National Sttrnlttondttetor Sales Supply Voltage (V00)
Offlce/Dlstrlbutors tor availability and apeelfleatltsna. Military 4.50 5.50 V
Supply Voltage (Note 2) -0.5V to + 7.0V Commercial 4.75 5.25 V
Input Voltage (Note 2) - 1.2V to + 5.5V Amt?” Temperature (TA)
Out tV It Not 2 -0.5Vt +55v Military -55 +125 'C
u pu o age( tt 9 ) 'a', o C, Commercial 0 + 70 °c
Storage Temperature -65 C to + 150 C Logical "O" Input Voltage 0 0.8 V
Lead Temp. (Soldering, 10 seconds) 300°C Logical "1 " Input Voltage 2.0 5.5 v
ESD to be determined.
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be permanently damaged. They do not mean that the device may
be operated at these vatues.
Note 2: These limits do not apply during programming. For the programming
ratings, refer to the programming instructions.
DC Electrical Characteristics (Note1)
Symbol Parameter Conditions DM77S184 DMB7S184 Units
Min Typ Max Mln Typ Max
‘IL Input Load Current Vcc = Max, VIN = 0.45V -80 -250 -80 -250 pA
IIH Input Leakage Current VCC = Max, VIN = 2.7V 26 25 p.A
Vcc = Max, VIN = 5.5V 1.0 1.0 mA
VOL Low Level OutputVoltage Vcc = Min, IOL = 16 mA 0.35 0.50 0.35 0.45 V
" Low Level Input Voltage 0.80 0.80 V
" High Level Input Voltage 2.0 2.0 V
loz Output Leakage Current Vcc = Max, chx = 2.4V 50 _ 50 FA
(Open-Collector Only) Vcc = Max, VCEX = 5.5V 100 100 P- A
VC InputClamp Voltage Vcc = Min, IN = ~18 mA -0.8 -1.2 -0.8 --1.2 V
ch InputCapacitance Vcc == 5.0V, VIN = 2.0V
TA = 25''C, 1 MHz 4.0 4.0 pF
Co Output Capacitance VCC = 5.0V. Vo = 2.0V 6 0 6 0 F
TA = 25''C, 1 MHz, Outputs Off . . p
ICC Power Supply Current Vcc = Max, Input Grounded 100 140 100 140 m A
All Outputs Open
Nola I: These limits apply over the entire operating range unless otherwise noted. All typical values are for Vcc = 5.0V and TA = 25°C.
AC Electrical Characteristics with Standard Load and Operating Conditions
COMMERCIAL TEMP RANGE (tPC to + 70''C)
JEDEC DM87S184 DM87S184A
Symbol S b I Parameter Units
ym tt Mln Typ Max Mln Typ Max
TAA TAVQV Address Access Time 40 55 30 45 ns
TEA TEVQV Enable Access Time 15 25 15 25 ns
TER TEXQX Enable Recovery Time 15 25 15 25 ns
MILITARY TEMP RANGE (- 55''C to + 125°C)
Symbol ie,'e,', Parameter DM77S184 DM77S184A Units
ym 0 Min Typ Max Mln Typ Max
TAA TAVQV Address Access Time 40 70 30 60 ns
TEA TEVQV Enable Access Time 15 30 15 30 ns
TER TEXQX Enable Recovery Time 15 30 15 30 ns
Functional Description
TESTABI LITY
The Schottky PROM die includes extra rows and columns of
tusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the program-
ming tests in the final product. A ROM pattern is also per-
manently fixed in the additional circuitry and coded to pro-
vide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and colurnrt-stMtyt circuits and functionality of input and an-
able gates. All test circuits are available at both water and
assembled device levels to allow 100% functional and para-
metric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PHOMs are subject-
ed to an on-going reliability evaluation by the Reliability As-
surance Department. These evaluations employ accelerat-
ed life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and ther-
mal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configura-
tions is excellent.
TlTANlUM-TUNGSTEN FUSES
National's Programmable Read-Onty Memories (PROMs)
feature titanium-tungsten (T i-W) fuse links designed to pro-
gram efficiently with only 10.5V applied. The high perform-
ance and reliability of these PROMs are the result of fabrica-
tion by a Schottky bipolar process. of which the titanium-
tungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V,
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce parasitics. The device is designed to ensure
that worst-case fuse operating current is low enough for
reliable Iong-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire oper-
ating ranges of VCC and temperature.
VSLSLBWOIVSlSLLWG
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM77S184J - product/dm77s184]?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
DM87S184AJ - productldm87s184a]?HQS=T|—nul|-null-dscatalog-df—pf—nuII-wwe
DM87S184AN - product/dm87s184an?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nuII-wwe
DM87S184V - product/dm87s184v?HQS=T|-nu|I-nuIl-dscatalog-df-pf-nulI-wwe
DM87S184N - product/dm87s184n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM87S184J - product/dm87s184]?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
DM77S184AJ - product/dm77s184a]?HQS=T|—nulI-null-dscatalog-df—pf—nuII-wwe
DM87S184AV - product/dm87s184av?HQS=T|—null-nulI-dscatalog-df-pf-nuII-wwe
