DM81LS95AWM ,TRI-STATE Octal BufferDM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal BufferSeptember 1991Revised May 1999DM81LS95A • DM8 ..
DM81LS96AN ,3-STATE Octal BufferDM74LS465(DM81LS95A)/DM74LS466(DM81LS96A)/DM74LS467(DM81LS97A)/DM74LS468(DM81LS98A)TRI-STATEOctalBu ..
DM81LS96N , Three-State Octal Buffers
DM81LS97AN ,3-STATE Octal BufferDM74LS465(DM81LS95A)/DM74LS466(DM81LS96A)/DM74LS467(DM81LS97A)/DM74LS468(DM81LS98A)TRI-STATEOctalBu ..
DM81LS97N , Three-State Octal Buffers
DM81LS97N , Three-State Octal Buffers
DS26C31E , CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER
DS26C31E , CMOS QUAD TRI-STATE DIFFERENTIAL LINE DRIVER
DS26C31M ,CMOS Quad TRI STATE Differential Line DriversFeaturesYTTL input compatibleThe DS26C31 is a quad differential line driver designed forYdigital da ..
DS26C31MJ/883 ,CMOS Quad TRI-STATE Differential Line DriverFeaturesDS26C31T meets all the requirements of EIA standardn TTL input compatibleRS-422 while retai ..
DS26C31MJ/883 ,CMOS Quad TRI-STATE Differential Line DriverDS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line DriverJune 1998DS26C31T/DS26C31M®CMOS Quad ..
DS26C31MW/883 ,CMOS Quad TRI-STATE Differential Line DriverGeneral Descriptiondischarge by diodes to V and ground.CCThe DS26C31 is a quad differential line dr ..
DM81LS95AWM
3-STATE Octal Buffer
DM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal Buffer September 1991 Revised May 1999 DM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal Buffer General Description Features These devices provide eight, two-input buffers in each � Typical power dissipation package. All employ low-power-Schottky TTL technology. DM81LS95A, DM81LS97A 80 mW One of the two inputs to each buffer is used as a control DM81LS96A 65 mW line to gate the output into the high-impedance state, while � Typical propagation delay the other input passes the data through the buffer. The DM81LS95A and DM81LS97A present true data at the out- DM81LS95A, DM81LS97A 15 ns puts, while the DM81LS96A is inverting. On the DM81LS96A 10 ns DM81LS95A and DM81LS96A versions, all eight 3-STATE � Low power-Schottky, 3-STATE technology enable lines are common, with access through a 2-input NOR gate. On the DM81LS97A version, four buffers are enabled from one common line, and the other four buffers are enabled form another common line. In all cases the outputs are placed in the 3-STATE condition by applying a high logic level to the enable pins. Ordering Code: Order Number Package Number Package Description DM81LS95AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM81LS95AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM81LS96AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM81LS96AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM81LS97AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions DM81LS95A and DM92LS96A Pin Names Descriptions A1–A8 Inputs Y1–Y8 Outputs Active LOW Output Enables (Note 1) G1–G2 Note 1: Both G1 and G2 must be LOW for outputs to be enabled. DM81LS97A Pin Names Descriptions A1–A8 Inputs Y1–Y8 Outputs Active LOW Output Enable (Y1–Y4) G1 Active LOW Output Enable (Y5–Y8) G2 © 1999 DS006435
