DM74S74N ,Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered D flip-flops with ..
DM74S86N ,Quad 2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic Excl ..
DM77S185J ,70 ns, (2048 x 4) 8192-bit TTL PROMFeatures
I Advanced titanium-tungsten (T i-W) fuses
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Address ac ..
DM81LS95AN ,3-STATE Octal BufferFeatureser. The ’LS465 and ’LS467 present true data at the outputs,YOctal versions of popular DM743 ..
DM81LS95AWM ,TRI-STATE Octal BufferDM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal BufferSeptember 1991Revised May 1999DM81LS95A • DM8 ..
DM81LS96AN ,3-STATE Octal BufferDM74LS465(DM81LS95A)/DM74LS466(DM81LS96A)/DM74LS467(DM81LS97A)/DM74LS468(DM81LS98A)TRI-STATEOctalBu ..
DS25BR400TSQ , Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization
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DS25CP152TSQ/NOPB ,3.125 Gbps LVDS 2x2 Crosspoint Switch 16-WQFN -40 to 85FEATURES DESCRIPTIONThe DS25CP152 is a 3.125 Gbps 2x2 LVDS2• DC - 3.125 Gbps Low Jitter, Low Skew, ..
DS25LV02R , Low-Voltage 1024-Bit EPROM
DS25MB100TSQ/NOPB ,2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization 36-WQFN -40 to 85(1)Pin Functions (continued)PIN(2)TYPE DESCRIPTIONNAME NO.DES_0 and DES_1 select the output pre-emp ..
DS26102 ,16-Port TDM-to-ATM PHYBlock Diagram.. 7 Figure 7-1. Polling Phase and Selection Phase at Transmit Interface........18 Fig ..
DM74S74N
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig- gered D flip-flops with complementary outputs. The infor- mation on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74S74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74S74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H L L X X H* H* HH ↑ HH L HH ↑ LL H HH L X Q Q 0 0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level ↑ = Positive-going Transition * = This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to its inactive (HIGH) level. Q = The output logic level of Q before the indicated input conditions were 0 established. © 2000 DS006457
