DM74S572AN ,45 ns, (1024 x 4) 4096-bit TTL PROMFeatures
Address access-M ns max
Enable access-N ns max
Enable recovery-25 ns max
I Advance ..
DM74S572N ,60 ns, (1024 x 4) 4096-bit TTL PROMBlock Diagram
DECDDER
ENABLE
GATE 03
40.53” ARRAY
M x 64
MEMORY MATRIX
Pin Names f _ ..
DM74S573AN ,45 ns, (1024 x 4) 4096-bit TTL PROMGeneral Description
This Schottky memory is organized in the popular 1024
words by 4 bits confi ..
DM74S573J ,60 ns, (1024 x 4) 4096-bit TTL PROMGeneral Description
This Schottky memory is organized in the popular 1024
words by 4 bits confi ..
DM74S573N ,60 ns, (1024 x 4) 4096-bit TTL PROMFeatures
I Advanced titanium-tungsten (T i-W) fuses
I Schottky-clamped for high speed
Addres ..
DM74S573N ,60 ns, (1024 x 4) 4096-bit TTL PROMBlock Diagram
WIT ARMY
M x M
MEMORY MATRIX
KGODER
W5 03 il? m a
Pin Names
A0-A9 Ad ..
DS25BR400TSQ , Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization
DS25BR400TSQ/NOPB ,Quad 2.5 Gbps CML Transceiver withTransmit De-Emphasis and Receive Equalization 60-WQFN -40 to 85Table 1. PIN DESCRIPTIONS (continued)(1)Pin Name Pin Number I/O DescriptionOB_0+ 55 O Inverting and ..
DS25CP152TSQ/NOPB ,3.125 Gbps LVDS 2x2 Crosspoint Switch 16-WQFN -40 to 85FEATURES DESCRIPTIONThe DS25CP152 is a 3.125 Gbps 2x2 LVDS2• DC - 3.125 Gbps Low Jitter, Low Skew, ..
DS25LV02R , Low-Voltage 1024-Bit EPROM
DS25MB100TSQ/NOPB ,2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-Emphasis and Receive Equalization 36-WQFN -40 to 85(1)Pin Functions (continued)PIN(2)TYPE DESCRIPTIONNAME NO.DES_0 and DES_1 select the output pre-emp ..
DS26102 ,16-Port TDM-to-ATM PHYBlock Diagram.. 7 Figure 7-1. Polling Phase and Selection Phase at Transmit Interface........18 Fig ..
DM74S572AN-DM74S572N
60 ns, (1024 x 4) 4096-bit TTL PROM
DM54/743572
National
Semiconductor
DM54/74S572
(1024 x 4) 4096-Bit TTL PROM
General Description
This Schottky memory is organized in the popular 1024
words by 4 bits configuration. Memory enable inputs are
provided to control the output states. When the device is
enabled, the outputs represent the contents of the selected
word. When disabled, the 4 outputs go to the "OFF" or high
impedance state.
PROMs are shipped from the factory with lows in all loca-
tions. A high may be programmed into any selected location
by following the programming instructions.
Features
II Advanced titanium-tungsten (Ti-W) fuses
u Schottky-clamped for high speed
Address access-45 ns max
Enable aCcess-25 ns max
Enable recovery-25 ns max
I: PNP inputs for reduced input loading
a All DC and AC parameters guaranteed over
temperature
II Low voltage TRI-SAFETM programming
a Open collector outputs
Block Diagram
4096911 ARRAY
MEMORY MATRIX
UEBUDER
ENABLE
“TE 03 02 at no
Pin Names .. *
AO-AO Addresses
a E Output Enables
GN D G round
QO-QS Outputs
Vcc Power Supply
TL/D/9712-1
Connection Diagrams
Dual-ln-LIne-Package
M-rl I 18 "Vcc
M- 2 17 -A7
M- 3 16 --M
A3- 4 15 "-M
M- 5 14 -oo
Ale 6 13 ~01
hr- 7 12 -02
EI- a 11 -tl3
GND- 9 10 -c_2
TL/D/9712-2
Top View
Order Number DM54/74SS72J, 572AJ,
DM745572N, 572AN
See NS Package Number J18A or N18A
Ordering Information
Commercial Temp Range ttrc to + 7tt'C)
Parameter/Order Number
Max Access Tlme (ns)
DM74S572AJ 45
DM74SS72J 60
DM74S572AN 45
DM74S572N 60
DM74SS72AV 45
DM74S572V 60
Plastlc Leaded Chip Carrier (PLCC)
Q Q 2 ' tt
I I I l I
3 2 I 2019
A4-4 18-h8
A3-5 17-M
AO-S 16-00
AI-7 Irs).-;
A2-8 t4-01
' IO 11 12 13
I I I l I
M a Is 3 8
TL/D/9712-3
Toleew
Order Number DM745572V, 572AV
See NS Package Number V20A
Military Temp Range t-- 55'C to + 125°C)
Parameter/Order Number Max Access Time (ns)
DM54S572AJ 60 .. _
DM548572J 75
ZLSSWJVSWCI
DM54/ 748572
Absolute Maximum Ratings (Note1) Operating Conditions
It Mllitary/Aerospace speeitled devices are required, Mln Max Unite
33755973333312.350.232323'.ny522‘§°§§§§%?;Ioi?“ 8“?” Voltage (Vcc)
. Military 4.50 5.50 V
Supply Voltage (Note 2) -0.5 to + 7.0V Commercial 4.75 5.25 V
Input Voltage (Note 2) - 1.2V to + 5.5V Ambient Temperature (TA)
Output Voltage (Note 2) - 0.5V to + 5.5V Military - 55 + 125 (
Storage Temperature -65''C to + 150°C Commercial 0 + 70 ''C
Lead Temp. (Soldering, 10 sec.) 300'C Logical "ty' Input Voltage 0 0.8 V
ESD to be determined Logic "I '' Input Voltage 2.0 5.5 V
Note l.. Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming instructions.
DC Electrical Characteristics (Note1)
Symbol Parameter Conditions DM54S572 DM74S572 Units
Min Typ Max Min Typ Max
IIL Input Load Current Vcc = Max, N/IN = 0.45V -80 -250 -80 -250 p.A
IIH Input Leakage Current Vcc = Max, VlN = 2.7V 25 25 p.A
Vcc = Max,v.N = 5.5V 1.0 1.0 mA
VOL Low Level Output Voltage Vcc = Min, 'OL = 16 mA 0.35 0.50 0.35 0.45 V
" Low Level Input Voltage 0.80 0.80 V
" High Level Input Voltage 2.0 2.0
'02 Output Leakage Current Vcc = Max, VCEX = 2.4V 50 50 0A
(Open-CollectorOnly) Vcc = Max, VCEX = 5.5V 100 100 “A
Vc Input Clamp Voltage VCC = Min, IN = -18 mA -0.8 -1.2 --0.8 .r -1.2 V
C, lnputCapacitance "fr, 2:“gv'1vf‘l/INHZ 2.0V 4.0 4.0 pF
Co OutputCapacitance Vcc = 5.0V, Vo = 2.0V 6.0 6.0 pF
TA = 2S'C, 1 MHz, Outputs Off
ICC Power Supply Current Vcc = Max, Input Grounded 100 140 100 140 mA
All Outputs Open
Note 1: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vcc = 5.0V and TA = +25°C.
AC Electrical Characteristics (With Standard Load and Operating Conditions)
COMMERCIAL TEMP RANGE (ty'G to + 70°C)
DM745572 DM745572A
Symbol JEDEC Symbol Parameter . Units
Min Typ Max Mln Typ Max
TAA TAVQV Address Access Time 40 60 25 45 ns
TEA TEVQV Enable Access Time 20 35 15 25 ns
TER TEXQX Enable Recovery Time 20 35 15 25 ns
MILITARY TEMP RANGE (- 55''C to + 125°C)
DM548572 DMS4SS72A
Symbol JEDEC Symbol Parameter Units
Min Typ Max Min Typ Max
TM TAVQV Address Access Time 40 75 25 60 ns
TEA TEVQV Enable Access Time 20 45 15 35 ns
TER TEXQX Enable Recovery Time 20 45 15 35 ns
Functional Description
TESTABILITY
The Schottky PROM die includes extra rows and columns of
fusable links for testing the programmability of each chip.
These test fuses are placed at the worst-case chip locations
to provide the highest possible confidence in the program-
ming tests in the final product. A ROM pattern is also per-
manently fixed in the additional circuitry and coded to pro-
vide a parity check of input address levels. These and other
test circuits are used to test for correct operation of the row
and coiumn-seiect circuits and functionality of input and en-
able gates. All test circuits are available at both wafer and
assembled device levels to allow 100% functional and para-
metric testing at every stage of the test flow.
RELIABILITY
As with all National products, the Ti-W PROMs are subject-
ed to an on-going reliability evaluation by the Reliability As-
surance Department. These evaluations employ accelerat-
ed life tests, including dynamic high-temperature operating
life, temperature-humidity life, temperature cycling, and ther-
mal shock. To date, nearly 7.4 million Schottky Ti-W PROM
device hours have been logged, with samples in Epoxy B
molded DIP (N-package), PLCC (V-package) and CERDIP
(J-package). Device performance in all package configura-
tions is excellent.
TlTANIUM-TUNGSTEN FUSES
National's Programmable Read-Only Memories (PROMs)
feature titanium-tungsten (Ti-W) fuse links designed to pro-
gram efficiently with only 10.5V applied. The high perform.
ance and reliability of these PROMs are the result of fabrica-
tion by a Schottky bipolar process, of which the titanium-
tungsten metallization is an integral part, and the use of an
on-chip programming circuit.
A major advantage of the titanium-tungsten fuse technology
is the low programming voltage of the fuse links. At 10.5V.
this virtually eliminates the need for guard-ring devices and
wide spacings required for other fuse technologies. Care is
taken, however, to minimize voltage drops across the die
and to reduce paresitics. The device is designed to ensure
that woret-case fuse operating current is low enough for
reliable long-term operation. The Darlington programming
circuit is liberally designed to insure adequate power density
for blowing the fuse links. The complete circuit design is
optimized to provide high performance over the entire oper-
ating ranges of Vcc and temperature.
ZlSSfl/VSWG
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM74S572AV - product/dm74s572av?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM74S572J - product/dm745572j?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
DM54S572AJ - product/dm54s572aj?HQS=T|—nulI-null-dscatalog-df—pf—nuII-wwe
DM74S572AN - product/dm74s572an?HQS=T|-nu|I-null-dscatalog-df—pf-nuII-wwe
DM74S572AJ - product/dm74s572aj?HQS=TI-null-nulI-dscatalog-df-pf—nuII-wwe
DM74S572N - product/dm743572n?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuIl-wwe
DM74S572V - product/dm74s572v?HQS=T|-nu|I-nuIl-dscatalog-df-pf-nulI-wwe
DM54S572J - product/dm543572j?HQS=T|-nu|I-nulI—dscatalog-df—pf—nuII-wwe
