DM74S51N ,Dual 2-Wide 2-Input AND-OR-INVERT GateGeneral DescriptionThis device contains two independent combinations ofgates each of which performs ..
DM74S570AJ ,45 ns, (512 x 4) 2048-bit TTL PROMBlock Diagram
MIT ARRAY
M x Q
MEMORV MATRIX
DECDDER
mm
BUFFER ca 02 tll no
TL/D/91B9 ..
DM74S570N ,55 ns, (512 x 4) 2048-bit TTL PROMElectrical Characteristics (Note1)
Symbol Parameter Conditions DM545570 DM74S570 Units
Min Typ Ma ..
DM74S571AJ ,45 ns, (512 x 4) 2048-bit TTL PROMFeatures
I Advanced titanium-tungsten (Ti-W) fuses
I Schottky-clamped for high speed
Address ..
DM74S571AN ,45 ns, (512 x 4) 2048-bit TTL PROMBlock Diagram
20488” ARRAV
M l 32
MEMORY MATRIX
DECODER
ENABLE
BUFFER
00
TL/D/9713- ..
DM74S571J ,55 ns, (512 x 4) 2048-bit TTL PROMGeneral Description
This Schottky memory is organized in the popular 512
words by 4 bits config ..
DS2506 ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
DS2506S ,64 kbit Add-Only MemoryFEATURES PIN ASSIGNMENT 65536 bits Electrically Programmable ReadPR-35Only Memory (EPROM) communic ..
DS25BR400TSQ , Quad 2.5 Gbps CML Transceiver with Transmit De-Emphasis and Receive Equalization
DS25BR400TSQ/NOPB ,Quad 2.5 Gbps CML Transceiver withTransmit De-Emphasis and Receive Equalization 60-WQFN -40 to 85Table 1. PIN DESCRIPTIONS (continued)(1)Pin Name Pin Number I/O DescriptionOB_0+ 55 O Inverting and ..
DS25CP152TSQ/NOPB ,3.125 Gbps LVDS 2x2 Crosspoint Switch 16-WQFN -40 to 85FEATURES DESCRIPTIONThe DS25CP152 is a 3.125 Gbps 2x2 LVDS2• DC - 3.125 Gbps Low Jitter, Low Skew, ..
DS25LV02R , Low-Voltage 1024-Bit EPROM
DM74S51N
Dual 2-Wide 2-Input AND-OR-INVERT Gate
DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gate August 1986 Revised April 2000 DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gate General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Ordering Code: Order Number Package Number Package Description DM74S51N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Y = AB + CD Inputs Output AB CD Y HH X X L XX H H L All other H combinations H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level © 2000 DS006454
