DM74S195N ,7 V, 4-bit parallel access shift registerElectrical Characteristics over recommended operating free air temperature (unless otherwise noted) ..
DM74S20N ,Dual 4-Input NAND GateGeneral DescriptionThis device contains two independent gates each of whichperforms the logic NAND ..
DM74S240N ,Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesThese buffers/line drivers are designed to improve both the
DM74S195N
7 V, 4-bit parallel access shift register
National _
i Semiconductor
DM54S195/DM74S195 4-Bit Parallel Access
Shift Registers
General Description
These 4-bit registers feature parallel inputs, parallel outputs,
J-R serial inputs, shift/load control input, and a direct over-
riding clear. All inputs are buffered to lower the input drive
requirements. The registers have two modes of operation:
Parallel (broadside) load
Shift (in the direction 0A toward Go)
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control input low. The data is
loaded into the associated flip-flop and appears at the out-
puts after the positive transition of the clock input. During
loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load
control input is high. Serial data for this mode is entered at
the J-R inputs. These inputs permit the first stage to perform
as a J-R, D, or T-type flip-flop as shown in the truth table.
The high-performance S195, with a 105 MHz typical shift
frequency, is particularly attractive for very high-speed data
processing systems. In most cases existing systems can be
upgraded merely by using this Schottky-clamped shift regis-
Features
I: Synchronous parallel load
I: Positive-edge-triggered clocking
a Parallel inputs and outputs from each flip4lop
'' Direct overriding clear
a J and R inputs to first stage
n Complementary outputs from last stage
n For use in high-pertormance:
accumulators/processors
serial-to-parallel, paralleI-to-serial converters
a Typical clock frequency 105 MHz
', Typical power dissipation 350 mW
Connection Diagram
Dual-In-Llne Package
OUTPUTS
'r---------"------,
Vcc " 05 tttt
16 " " 13
- SHIFT
On thy CLOCK LOAD
1 2 a 4
CLEAR J R A
SERIAL INPUTS
12 I1 10 "
s G 7 8
B C D GND
PARALLEL INPUTS
TLlF/6476-1
Order Number DM545195J or DM745195N
See NS Package Number J16A or N165
Absolute Maximum Ratings (Note)
if Mllltary/Aerospace specltled devices are required,
please contact the National Setttlettndutttor Sales
oft1ttefDlgtributttrtt for availability and specifications.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54S --55''C to +125''C
Storage Temperature Range
0°C to + 7ty'C
-65°C to + 150''C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The de vice should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
tab/e are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table 'eil/ definty
the conditions for actual device operation.
Symbol Parameter DM54S195 DM74S195 Unlts
Mln Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current - 1 - 1 mA
lot. Low Level Output Current 20 20 mA
fCLK Clock Frequency (Note 1) 0 105 70 0 105 70 MHz
fCLK Clock Frequency (Note 2) 90 60 O 90 60 MHz
tw Pulse Width Clock 7
Note a) ns
( Clear 12 12
tsu Setup Time Shift/Load 11 1 1
(Note 3) Data 5
t... Data Hold Time (Note 3) 3 ns
tREL Shift/Load Release Time (Note 3) 6 ns
Clear Release Time (Note 3) 9
TA Free Air Operating Temperature - 55 125 0 70 'C
Note 1: CL = 15 pF, RL == 2309. TA = 25''C and Vcc = 5V.
Nate 2: Cc = 50 pF, RL = 28011,TA = 25'C and vcc = 5V.
Note & TA = 25°C and Vcr; = 5V.
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Condlllons Mln Typ Max Units
(Note 4)
V. lnputClamp Voltage Vcc = Min, II = -18 mA -1.2 V
VoH High Level Output Vcc = Min, IOH = Max DM54 2.5 3.4 V
VOL Low Level Output Vcc = Min, lot. = Max 0 5 V
Voltage " = Min, " = Max .
I. InputCurren1@ Max Vcc = Max, VI = 5.5V
Input Voltage
lm High Level Input Current Vcc = Max, V. = 2.7V 50 “A
lit. Low Level InputCurrent Vcc = Max, V. = 0.5V -2 mA
kos Short Circuit Vcc = Max DM54 --40 - 100 m A
Output Current (Note 5) DM74 - 40 --100
ICC Supply Current Vcc = Max (Note 6) 70 109 mA
Note & All typical: are at Vcc = 5V, TA = 25'C.
Note 5: Nat more than one output should be shorted at a time. and the duration should not exceed one second.
Note ik With all inputs open, SHIFT/LOAD grounded, and 4.5V applied to the J, K, and data inputs, Ice is measured by applying a momentary ground, then 4.5V to
the CLEAR and then applying a momentary ground then 4.5V to the CLOCK.
Switching Characteristics at Vcc == 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 280.0
From (Input) - _
s mbol Parameter c _ 15 F c - so F Units
y To (Output) L p L p
Mln Max Mln Max
fMAx Maximum Clock 70 60 MHz
Frequency
tpLH Propagation Delay Time Clock to 1 2 1 5 as
Low to High Level Output Any 0
tPHL Propagation Delay Time Clock to 1 6.5 20 ns
High to Low Level Output Any Q
tpHL Propagation Delay Time Clear to
High to Low Level Output Any O 16.5 23 ns
Function Table
Inputs Outputs
t rl I
Clear iii"; Clock So a Parallel 0A th, 0c QD tio
Ott J R A a c D
L X X X X X X X X L L L L H
H L t x x a b e d a b c d a
H H L X X X X X X 0A0 tho Qco thoo 600
H H t L H X X X X QAO (DAO 03,, thy, tkr,
H H t L L x x x x L tu, ther, thm Coo,
H H t H H X X X X H tu, 03,, QCn C2cr,
H H t H L X X X X TU, QAn thm Ocn 60,,
H = High Level (steady state), L " Low Level (steady state), X a Don't Care (any input, including transitions)
t = Transition from low to high level
s, b, c, d = The level of steady state input at A, B, C, or D, respectively.
' 050. Goo. thoo = The level of GA. thr thy or 00, "rspectMsty, before the indicated steady state input conditions were established.
Ro,, thr,, Con - The level of 0A. ths, QC, respectiveiy, before the most recent transition of the clock.
Logic Diagram
SERIAL
INPUT PARALLEL Inputs
J R A a c o"
SHIFT/LOAD (g) (2) ta) (4) (5) (a) (1)
CONTROL
CLOCK "o'] y: '-
CLEAR =1» 1 I i 1
CLEA_R L CLEAR CLEAR CLEAR
l [ Lcd', cg: -e,'lcoo, >RCLOCK Lcxot,',
'""t'i--i,sr
-u'2""2i; 1rA 15) (14) (13) "I
tht the O; (12,0000
PARALLEL ouwurs
TL/F/6476-2
Timing Diagram
Typlcal Clear, Shift, and Load Sequences
INPUTS
SERIAL {J
SMI FT / LOAD
PARALLEL
INPUTS
SERIAL SHIFT SERIAL SMtFT-------
TL/Fl6478-3
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DM54S195J - product/dm54s195]?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
DM74S195N - product/dm74s195n?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuIl-wwe
