DM74S181N ,7 V, arithmetic logic unit/function generatorapplications data for the
DM54S182/DM748182. (Continued)
Connection Diagram Pin Designations
Dua ..
DM74S181N ,7 V, arithmetic logic unit/function generatorGeneral Description (Continued)
if high speed is not important, a ripple-carry input (Cn) and a
..
DM74S181N ,7 V, arithmetic logic unit/function generatorGeneral Description
These arithmetic logic units (ALU)/function generators per-
form 16 binary ..
DM74S182N ,Look-Ahead Carry GeneratorGeneral Description
These circuits are high-speed, look-ahead carry generators,
capable of anti ..
DM74S188AN ,25 ns, (32 x 8) 256-bit TTL PROMElectrical Characteristics (Note 3)
Symbol Parameter Condltlons DMMS‘“ DM74S188 Units
IIL Input L ..
DM74S188N ,35 ns, (32 x 8) 256-bit TTL PROMBlock Diagram
WIT MIN"
32 x 8
MEMORY MATRIX
mm
aumn il?
Pln Names
AO-M
m OutputEnab ..
DS2482-100+ ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterFEATURES The DS2482-100 is an I²C to 1-Wire bridge device I²C Host Interface, Supports 100kHz ..
DS2482S-100+ ,Single-Channel 1-Wire Masterfeatures with an output to control an external 8-Pin, 150-mil SO Package MOSFET for enhanced str ..
DS2482S-800 ,Eight-Channel 1-Wire MasterAPPLICATIONS PART TEMP RANGE PIN-PACKAGE Wireless Base Stations DS2482S-800 -40 to +85C 16 SO ( ..
DS2482X-101+T , Single-Channel 1-Wire Master with Sleep Mode
DM74S181N
7 V, arithmetic logic unit/function generator
National _
1 Semiconductor
DM54S181/DM74S181 Arithmetic Logic
Unit/Function Generators
General Description
These arithmetic logic units (ALU)/function generators per-
form 16 binary arithmetic operations on two 4-bit words, as
shown in Tables 1 and 2. These operations are selected by
the four function-select lines (SO, Sl, S2, S3) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal car-
ries must be enabled by applying a Iow-level voltage to the
mode control input (M). A full carry Iook-ahead scheme is
available in these devices for fast, simultaneous carry gen-
eration by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM54S182/DM74S182 full carry look-ahead circuits, high-
speed arithmetic operations can be performed. The typical
addition times shown below illustrate how little time is re-
quired for addition of longer words, when full carry look-
ahead is employed. The method of cascading 182 circuits
with these ALU's to provide multi-Ievel full carry look-ahead
is illustrated under typical applications data for the
Features
a Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations
I: Logic function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
I: Full look-ahead for high-speed operations on long
DM54S182/DM74S182. (Continued)
Connection Diagram Pin Designations
DuaI-In-Llne Package Deslgnatlon Pln Nos. Functlon
NPUTS OUTPUTS
'" ' = , ,_ A " A3,Ai?,At,A0 19,21,23,2 WordAlnputs
VCC At BI A2 B2 A3 as G en“ P A=B F3
I I I I I I I I I I B3, B2, B1, BO 18, 20, 22, 1 Word B Inputs
24 23 22 21 20 " " " " " " "
- S3, S2, S1, SO 3, 4, 5, 6 Function-Select
Cn 7 lnv. Carry Input
M 8 Mode Control
F3, F2, F1, F0 13, 11, 10, 9 Function Outputs
A = B 14 ComparatorOutput
" T T P 15 Carry Propagate
- Output
ll I2 3 4 5 6 7 8 I9 |10|11l12 Cn+4 16 lnv.CarryOutput
BO A0 S3 sa SI so Cn M F0 F1 F2 GND
t V 1 L l G 17 Carry Generate
INPUTS OUTPUTS Output
TL/F/6473-1 S I
Order Number DM54S181J or nwmsmm Vcc 24 upply Vo tage
See NS Package Number J24A or N24A GND 12 Ground
General Description (Continued)
if high speed is not important, a rippIe-carry input (Cn) and a
rippIe-carry output (On+4) are available. However, the rip-
ple-carry delay has also been minimized so that arithmetic
manipulations for small word lengths can be performed
without external circuitry.
These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown below.
Subtraction is accomplished by I's complement addition,
where the I's complement of the subtrahend is generated
internally. The resultant output is A-B-I, which requires
an end-around or forced carry to provide A--B.
The S181 can also be utilized as a comparator. The A = B
output is internally decoded from the function outputs (FO,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The A
= B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (Cn+ 4) can also be used to supply
relative magnitude information. Again, the ALU should be
placed in the subtract mode by placing the function select
inputs SS. S2, SI, so at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requriements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select in-
puts (SO, SI, Si?, S3) with the mode-control input (M) at a
high level to disable the internal carry. The 16 logic func..
tions are detailed in Tables 1 and 2 and include exclusive-
OR, NAND, AND, NOR, and OR functions.
ALU SIGNAL DESIGNATIONS
The DM54S181/DM74S181 can be used with the signal
designations of either Figure f or Figure 2.
The logic functions and arithmetic operations obtained with
signal designations as in Figure 1 are given in Table l; those
obtained with the signal designations of Figure d? are given
in Table ll.
Number Typical Package Count Carry Method
of Addition Times Arithmetic/ Look Ahead Betwe'en
Bits Logic Units Carry Generators ALU 3
1 to 4 20 ns 1 0 None
5 to 8 30 ns 2 0 Ripple
9 to 16 30 ns 3 or 4 1 Full Look-Ahead
17 to 64 50 ns 5 to 16 2 to 5 Full Look-Ahead
Pin Number 2 1 23 22 21 20 19 18 9 10 11 t3 7 16 15 "
Active-High Data (T able l) A0 Bo A1 B1 A2 Bi? A3 M F0 F1 F2 F3 Cr, Cn+4 X Y
Active-Low Data (Table li) M ED A1 Bl M Bg M B3 po Fl F2 F3 G, Cn+4 p 5
input Output Active-High Data Active-Low Data
On Cn + 4 (Figure 1) (Figure 2)
H H A s B A s B
H L A s B A s B
L H A S B A s B
L L A s B A s B
General Description (Continued)
(2) ill (23) (22) (21) (20) (19) (18)
A0 M At B1 A2 B2 A3 B3
(7) th,
5181 A = a - (14)
F0 F1 F2 F3 0...“ y x
(9) (10) (11) (13) (16) (1ry (IS)
(3) IA) (1) (2) (14) (15) (5) "i'
YO " Pt XI Y2 " " A3
x -ir)
a-o Cn 3182
y -t10)
cn+x crH-y cn+z
(12) (11) (9)
TL/F/6473-2
FIGURE 1
TABLEI
Active High Data
Selecllon
M = H M = L; Arithmetic Operations
S3 S2 SI so Functions Cn = H (no carry) th, = L(wlth carry)
L L L L F--A F=A F=APIus1
L L L H F=A+B F=A+B F--(A+B)PlusI
L L H L F=m F--A+g F--tA+B)Plus1
L L H H F = 0 F = Minus 1 (2's Compl) F = Zero
L H L L F---ht2- F=APlusA§ F=APlusA§P|us1
L H L H F--B F=(A+B)PlusA§ F=(A+B)PlusA§PIus1
L H H L F=AeB F=AMinusBMinus1 F=AMInusB
L H H H F=At3 F=A§Minus1 F---M
H L L L F--A+B F=APIusAB F=APIusABPIus1
H L L H F---AeB F---APlusB F=APlusBPlus1
H L H L F=B F=(A+§)PIusAB F=(A+§)PlusABPlus1
H L H H F--=AB F=ABMinus1 F=AB
H H L L F=1 F=APIusA' F=APlusAPlus1
H H L H F=A+§ F=(A+B)PlusA F=(A+B)PlusAPlus1
H H H L F=A+B F=(A+§)PlusA F---tA+tTyPiusAPlus1
H H H H F=A F=AMinus1 F=A
'Each bit is shifted to the next more significant position.
General Description (Continued)
(2) (1) (231(22) (21H20) (19H1B)
A0 BO A1 B1 A2 B2 A3 B3
5181 Ar--B--tt4)
F0 Ft F2 F3 cw... G P
(9) Ito) (11) (13) (15) (17 its)
(3) (4) (1) (2) (14H15) Ci) (6)
Go P0 GI P1 G2 P2 G3 P3
P D-- (7)
(13) Cn 5182
G cy- (10)
cn+x Cn+y cn+z
(12) (11) (l)
TL/F/64N-3
FIGURE 2
TABLE II
Active Low Data
Selection
M = H M = L;Arlthmatlc Operations
S3 S2 SI so Functions G, = Lino carry) on = H (wlth carry)
L L L L F---A F=AMinus1 F=A
L L L H F--M F=ABMinus1 F=AB
L L H L F--A+B F=A§Minus1 F=AB
L L H H F = 1 F = Minus 1 (2's Compl) F = Zero
L H L L F=A+B F=APIus(A+§) F=APlustA+B)Pks1
L H L H F==tT F=ABPlus(A+B) F=ABPlus(A+§)Plus1
L H H L F--AOB F=AMinusBMinus1 F=AMinusB
L H H H F----A+g F=A+§ F=(A+§)Plus1
H L L L F=KB F=APlus(A+B) F=APIus(A+B)Plus1
H L L H F=A$B F=APlusB F=APlusBPlus1
H L H L F=B F=A§Plus(A+B) F=A§Plus(A+B)Plus1
H L H H F=A+B F=A+B F=(A+B)Plus1
H H L L F=0 F=APlusA‘ F=APIusAPlus1
H H L H F--A+Ag F=ABPlusA F=ABP|usAPlus1
H H H L F = AB F = M PlusA F ---Ag PIusAPlus1
H H H H F=A F=A F=APlus1
'Each bit is shifted to the next more significant position.
Absolute Maximum Ratings (Note)
If Military/Aerospace speclfled devlces are required,
please contact the Natlonal Serttlttttrtdutttttr Sales
WflttttfDltttrlttutttrtt for ttvalttthlllty and trpet0eatlonB.
Supply Voltage 7V
Input Voltage 5.5V
Output Voltage (A == B Output) 5.5V
Operating Free Air Temperature Range
-55T to + 125'C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The dew'ce should notbe operatedat these limits. The
pararmstric values defined in the ''Eitatgttitttg Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Rtytxymmended Operating Conditions " table will define
the conditions for actual device operation.
Storage Temperature Range
trc to + 7tPC
-65°C to +150°C
Recommended Operating Conditions
Symbol Parameter DM54S181 DM74S181 Unlu
Min Nam Max Mln Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
VOH High Level Output
Voltage (A = B Output) 5.5 5.5 V
IOH High Level Output _ 1 -1 m A
Current(AlI ExceptA = B)
IOL Low Level Output Current 20 20 mA
TA Free Air Operating _ .
Temperature 55 125 0 70 0
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Condltlons Mln Typ Max Unlts
(Note 1)
V. InputClamp Voltage Vcc = Min, " = --18 mA -1.2 V
lch High Level Output Vcc = Min, Vo = 5.5V 250 PA
Current (A = B Output) " = Max,V|H = Min
VOH High LevelOutput Vcc = Min, km = Max DM54 2.5 3.4 V
Voltage (All ExceptA = B) " = Max, VIH T..= Min DM74 2.7 3.4
VOL Low Level Output Vcc = Min, IOL = Max 0 5 V
Voltage VIH = Min, " = Max .
I. InputCurrent @ Max Vcc = Max, V. = 5.5V
Input Voltage
IIH High Level Input VCC = Max Mode 50
Current lh = 2.7V A Or B 150
Carry 250
I.L Low Level Input Voc = Max Mode --2
Current v, = 0.5V _
A or B 6 m A
Carry -10
los Short Circuit Output Current VCC = Max (Note 2) _ _
(Any Output ExceptA = B) 40 100 mA
'00 Supply Current VCC = Max (Note 3) 120 220 mA
Note 1: All typicals are at Vcc - 5V, TA = 25'0.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note & Ice is measured tor the following conditions: A. so through S3, M, and A inputs at 4.5V, all other inputs grounded and all outputs open. B, SO through S3
and M inputs at 4.5V, all other inputs grounded and all outputs open.
Switching Characteristics VCC = 5V, TA = 25°C (See Section 1 for Test Waveforms and Output Load)
DM54/74
From To S181
Symbol Parameter Conditions (Input) (Output) RL = 2800, EL = 280tt, Units
CL=15PF CL=5OPF
Min Max Min Max
tpLH Propagation Delay Time, 10 5 14
Low-to-High Level Output Cr, Cn + 4 ns
tpHL Propagation Delay Time, 10 5 14
High-to-Low Level Output .
tpLH Propagation Delay Time, M = 0V, so = 18 5 22
Low-to-High Level Output S3 = 4.5V AnyA .
S1 = Sit = ov orB Cn+4 "
tPHL Propagation Delay Time, tTON d 18 5 22
High-to-Low LevelOutput ( mo ta) .
tpLH Propagation Delay Time, M = OV, so = 23 27
Low-to-High Level Output 83 = 0V AnyA
SI=S2--4.5V orB Cn+4 ns
tpHL Propagation Delay Time, t5fF7 d . 23 27
High-to-Low LevelOutput ( mo ta)
tpLH Propagation Delay Time, M _
. - 0V 12 14
Low-to-High Level Output (SUM or Cn Any F n s
tpHL Propagation Delay Time, DIFF mode) 12 14
High-to-Low Level Output
tpLH Propagation Delay Time, M == ov, so = 12 15
Low-to-High Level Output S3 = 4.5V AnyA
SI = S2 = OV or B G ns
tPHL Propagation Delay Time, 'stJh'f od 12 15
High-to-Low LevelOutput ( m e)
tpLH Propagation Delay Time, M = ov, SO = 15 19
Low-to-High Level Output S3 = 0V Any A G
. . SI = S2 = 4.5V orB ns
tpHL Propagation Delay Time, 5W5 d 15 20
High-to-Low LevelOutput ( mo e)
tpLH Propagation Delay Time, M = 0V, SO = 12 15
Low-to-High Level Output S3 = 4.5V AnyA P
. . S1 = S2 = 0V or B ns
tPHL Propagation Delay Time, SU_M od 12 15
High-to-Low Level Output ( m e)
tpLH Propagation Delay Time, M = 0V, so = 15 19
Low-to-High Level Output S3 = 0V AnyA
s1=sz=4sv orB P ns
tpHL Propagation Delay Time, DOT" d . 15 20
High-to-Low LevelOutput ( mo e)
tpLH Propagation Delay Time, M = 0V, SO = 16 5 20
Low-to-High Level Output S3 = 4.5V Ai or Bi Fi ' ns
. . S1 = S2 = 0V
tPHL Propagation Delay Time, -
High-to-Low Level Output (SUM mode) 16.5 20
tPLH Propagation Delay Time, M = ov, so = 20 24
Low-to-High Level Output S3 = 0V A or ih Pi
. . St = S2 = 4.5V rls
tPHL Propagation Delay Time, DI-FF: d 22 24
High-to-Low LeveIOutput ( mo e)
tpLH Propagation Delay Time, 20 24
Low-to-High Level Output M = 4.5V A or Bi F, ns
tPHL Propagation Delay Time, (logic mode) 22 24
High-to-Low Level Output
tpLH Propagation Delay Time, M = 0V, so = 23 26
Low-to-High Level Output S3 = 0V Any A A _ B
. ' s1=sz=45v orB _ ttS
tPHL Propagation Delay Time, 7? d 30 33
High-to-Low LeveIOutput ( mo e)
Parameter Measurement Information
Logic Mode Test Table
Furttttlonmputtr.S1 = S2 = M = 4.5V, so = S3 = 0V
Input Other Input Other Data Inputs Output
Same Blt Output
Parameter Under Under Waveform
Test Apply Appty Apply Apply Test
4.5V GND 4.5V GND
tPLH Ai Bi None None Remaining Fi Out-of-Phase
t A and B, G,
tPLH Bi Ai None None Remaining Fi Out-of-Phase
t A and B, Cn
SUM Mode Test Table
Function Inputszso = S3 = 4.5V,S‘l == S2 = M = 0V
Input tl',',',',,,''',,'),'' Other Data Inputs Output o
Parameter Under Under d,',',' J“; rm
Test Apply Apply Apply Apply Test
4.5V GND 4.5V GND
tpLH . . Remaining . -
t A. B. None A and B G, Fi In Phase
t Remainin
i-',',)-,'," Bi Ai None A and 89 On Fi In-Phase
tPLH Ai Bi None None Remaining P In-Phase
t A and B, th,
tPLH Bi A; None None Remaining P ln-Phase
t A and B, Cn
tpLH Ai None Bi Remaining Remaining G in-Phase
t B A, on
tpLH Bi None Ai Remaining Remaining G ln-Phase
t B A, On
tpLH All All Any F -
t ' None None A B or Cn + 4 In Phase
tPLH A; None Bi Remaining Remaining Cn + 4 Oubof-Phase
t B A, G,
tPLH Bi None A Remaining Remaining Cn + 4 Out-of-Phase
tPHL B AG,
Parameter Measurement Information (Continued)
DiFF Mode Test Table
Functlon Inputs: SI = S2 = 4.5V, so = B3 = M = 0V
Input Itll',',,',,''',,'','," Other Data Inputs Output Out ut
Parametet Under Under Wave: rm
Test Apply Apply Apply Apply Test tt
4.5V GND 4.5V GND
-.._..t..t.,'..L.tL., A None Bi "mtining 'trt,"' Fi In-Phase
tPHL ' n
-Ln,ri.,,..... Bi A None Remzmmg 'trt,"' Fi Out.of-Phase
tPHL a n
-......dreA, A None Bi None Ea"??? P In-Phasa
‘PHL an ' n
___._;t”-H__ Bi Ai None None Jegt1t P Out-of-Phase
tPHL ' n
__L‘-H._ A BI None None 522?; 2 G ln-Phase
tPHL , n
_tm_.H._. Bi None A, None je'gt2, G Out-of-Phase
tpre ' n
tPLH AI None Bi Remilnmg Reanegmng A = B ln-Phase
tPHL , n
tPLH Bi Ai None Remi'mng Reg?” A = B Out-of-phase
tPHL ' n
tpLH All Cn+4
tpHL Cn None None A and B None or any F In-Phase
tpLH Remaining
A th None None A B C Cn+4 Out-of-Phase
tPHL ' ' n
-tt'Lr_t., ih None A None Rszalrgng Cn + 4 In-Phase
tPHL ' ' n
Logic Diagram
s, l l
=i2Dr,at
vcc = PIN 24
GND = PIN 12
TUF/6473-4
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
DM74S181 N - product/dm74s181n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM54S181J - product/dm54s181j?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
