DM74S175N ,Hex/Quad D Flip-Flop with ClearApplications include:
Butter/storage registers
Shift registers
Pattern generators
I Typical c ..
DM74S181N ,7 V, arithmetic logic unit/function generatorapplications data for the
DM54S182/DM748182. (Continued)
Connection Diagram Pin Designations
Dua ..
DM74S181N ,7 V, arithmetic logic unit/function generatorGeneral Description (Continued)
if high speed is not important, a ripple-carry input (Cn) and a
..
DM74S181N ,7 V, arithmetic logic unit/function generatorGeneral Description
These arithmetic logic units (ALU)/function generators per-
form 16 binary ..
DM74S182N ,Look-Ahead Carry GeneratorGeneral Description
These circuits are high-speed, look-ahead carry generators,
capable of anti ..
DM74S188AN ,25 ns, (32 x 8) 256-bit TTL PROMElectrical Characteristics (Note 3)
Symbol Parameter Condltlons DMMS‘“ DM74S188 Units
IIL Input L ..
DS2482+100 ,Single-Channel 1-Wire MasterFEATURES The DS2482-100 is an I²C to 1-Wire bridge device I²C Host Interface, Supports 100kHz ..
DS2482-100+ ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterAPPLICATIONS DS2482S-100 -40 to +85C 8 SO (150 mil) Printers DS2482S-100/T&R 8 SO (150 mil) -4 ..
DS2482S-100 ,Single-Channel 1-Wire MasterFEATURES The DS2482-100 is an I²C to 1-Wire bridge device I²C Host Interface, Supports 100kHz ..
DS2482S-100+ ,Single-Channel 1-Wire Masterfeatures with an output to control an external 8-Pin, 150-mil SO Package MOSFET for enhanced str ..
DS2482S-800 ,Eight-Channel 1-Wire MasterAPPLICATIONS PART TEMP RANGE PIN-PACKAGE Wireless Base Stations DS2482S-800 -40 to +85C 16 SO ( ..
DM74S174N-DM74S175N
7 V, hex/quad D flip-flop with clear
National _
Semiconductor
DM54S174/DM74S174, DM54S175/DM74S175
Hex/Quad D Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type tlip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-tlop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particu-
lar voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the D input signal has no effect
atthe output.
Featu res
u S174 contain six flip-flops with single-rail outputs.
I: S175 Contain four flip-flops with double-rail outputs.
a Buffered clock and direct clear inputs
II Individual data input to each flip-tlop
II Applications include:
Buffer/storage registers
Shift registers
Pattern generators
a Typical clock frequency 110 MHz
a Typical power dissipation per flip-flop 75mW
Connection Diagrams
DuaHn-Llne Package
Vcc 06 D6 DS 05 04 04 CLOCK
'16 IS 14 13 12 11 10 9
Dual-ln-Llne Package
Vcc 04 64 04 D3 63 03 ca.ocx
I16 I15 " 13 " I11 I10 "
< C, : A A
I 1 2 3 4 5 6 7 I a I , I 2 I 3 4 5 I s I , Ia
CLEAR tyt D1 D2 02 D3 03 GND CLEAR Q1 61 D1 D2 62 02 GND
TL/F/6472-t
TL/F/M72-2
Order Number DM54S174J, DM54S175J, DM54$175W, DM745174N or DM748175N
See NS Package Number J16A, N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Clear Clock
Outputs
D a th
X 00 CK
H = High Level (steady state)
L -- Low Level (steady state)
X = Don't Care
t = Transition trom low to high level
th = The level of Q before the indicated steady-state input conditions were established
t = S175 only
SLlSOVll-S
Absolute Maximum Ratings (Note)
If MllltarWAerttsptttttt specified devices are required.
please contact the National Semiconductor Sales
offlttqVDltgtrittutttrs for avallablllty and speclflcatlons.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM548 -55''C to + 125°C
DM74S 0''C to + 70'C
Storage Temperature Range -65"C to + 150°C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guttran-
teed. The device should not be operated at these limits. The
parametric values defined in the "Etetttrittal Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions See Section1 for TestWaveformsand Output Load
Symbol Parameter DM54S174 DMNS1 " Urtlttt
Mln Nam Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
" High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
lor, High Level Output Current --1 -1 mA
10L Low Level Output Current 20 20 mA
‘CLK Clock Frequency (Note 1) 0 1 10 75 1 1O 75 MHz
fCLK Clock Frequency (Note 2) 90 65 90 65 MHz
tw Pulse Width Clock 7
(Note I) Clear 10 IO
Pulse Width Clock 9 9 ns
(Note 2) Clear 12 12
tsu Data Setup Time (Note 1) 5 5 ns
Data Setup Time (Note 2) 7 7
tH Data Hold Time (Note 1) 3 3
Data Hold Time (Note 2) 5 5 ns
tREL Clear Release Time (Note 1) 5 5 ns
Clear Release Time (Note 2) 7 7
TA Free Air Operating Temperature - 55 125 0 70 ''C
Holt 1:CL = 15 pF. RL " 2800. TA = 25% and Vcc = 5V.
Not. chL = 50 pF, RL -- 2800, TA = 25'0 and Vcc = 5V.
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Condltlons Mln (Note " Max Units
V. Input Clamp Voltage VCC = Min, II = -18 mA -1.2 V
VOH High Level Output Vcc = Min, loH = Max DM54 2.5 3.4 V
Voltage " = Max, VIH = Min DM74 2.7 3.4
VOL Low Level Output Vcc = Min, IOL = Max o 5 V
Voltage VIH = Min, VIL = Max .
II InputCurrent@ Max Vcc = Max,1h = 5.5V
Input Voltage
IIH High Levelinput Vcc = Max,1h = 2.7V 50 “A
Current
IIL Low Level Input Vcc = Max, V. = 0.5V --2 m A
Current
los Short Circuit Vcc -- Max DM54 -40 - 100
O t utCurrent (Note 2) mA
ll p DM74 -40 - 100
be Supply Current Vcc = Max
(S174) (Note 3) 90 144 mA
ICC Supply Current Vcc = Max
(S175) (Note 3) 60 96 mA
Switching Characteristics at Vcc = 5V and TA = 25''C (See Section 1 for Test Waveforms and Output Load)
RL = Mon
From (Input) - -
Symbol Parameter To (Output) th. 15 pF CL - 50 pF Units
Mln Max Mln Max
fMAX Maximum Clock Frequency 75 65 MHz
tpLH Propagation Delay Time Clock to 1 2 15 ns
Low to High Level Output Output
tPHL Propagation Delay Time Clock to 17 21 ns
High to Low Level Output Output
tPLH Propagation Delay Time
Low to High Level Output "T to 15 18 ns
(S175 Only)
tPHL Propagation Delay Time Clear
High to Low Level Output to to 22 23 ns
Note It All typical: are at Vcc = 5V, TA 2 25°C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open and 4.5V applied to all DATA and CLEAR inpuis. Ice is measured after a momentary ground, then 4.5V applied to the CLOCK input.
SUSOVUS
Logic Diagrams
tMo------------
>CLocx
>CLOCK
>CLOCK
*--0 03
"r"TU.'l,
D 0 O4
> CLOCK
',,-,,l,IL2'
D Q --o 05
CLOCK =tys----l
>CLOCK
--Ttts,
-Otttt
CLEAR cet-s--)'
TL/F/6472-3
>CLOCK
CLE AR
y CLOCK
>CLOCK
CLOCK c (9) Dr
CLEAR o-''at>cs-
>CLOCK
TL/ F/6472-4
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM74S175N - product/dm74s175n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM54S174J - product/dm54s174]?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
DM54S175J - product/dm54s175]?HQS=T|—nu|I-nulI-dscatalog-df—pf—nuII-wwe
DM54S175W - product/dm54s175w?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuIl-wwe
DM74S174N - product/dm74s174n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
