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DM74S113N
7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset and complementary output
National
Semiconductor
DM54S113/DM74S113 Dual Negative-Edge-Triggered
Master-Slave J-K Flip-Flops with Preset
and Complementary Outputs
General Description
This device contains two independent negative-edge-trig- negative going edge of the clock pulse. Data on the J and K
gered J-K flip-flops with complementary outputs. The J and inputs may be changed while the clock is high or low without
K data is processed by the tlip-flops on the falling edge of affecting the outputs as long as setup and hold times are
the clock pulse. The clock triggering occurs at a voltage not violated. A low logic level on the preset input will set the
level and is not directly related to the transition time of the outputs regardless of the logic levels of the other inputs.
Connection Diagram
Dual-In-Llne Package
ltcc CLKZ " J2 PR 2 oz 02
I14 13 12 ll Inn i, a
, l I 3 I 4 I 5 s I 7
tlt KI JI Pm ill lit GND
Function Table
TL/F/6460-1
Order Number DM54S113J or DM748113N
See NS Package Number J14A or N14A
Inputs Outputs
PR CLK J K o Ft
L X X X H L
H l L L Op th
H l H L H L
H l L H L H
H l H H Toggle
H H x x 00 60
H = High Logic Level
X = Either Low or High Logic Level
L ate Low Logic Level
L = Negative going edge of pulse,
th == The output logic level of 0 before the indicated input conditions were established.
Toggle = Each output changes to the complement of its previous Ievet on each falling edge ot the clock pulse.
Absolute Maximum Ratings (Note)
If MllltaryfAttrrtapttee specified devlces are required,
please contact the National Semlttondutttor Sales
omtNtmtatrlttuttmt for availability and Bpeeltieatlttrte.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54S -55'C to + 125°C
DM74S ty'C to + 70°C
Storage Temperature Range -65'C to + 150°C
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should natbe operated at these limits. The
parametric values darned in the "Electrical Ghttrattttrritttics''
table are not guaranteed at the absolute maximum ratings.
The "Rmxymmtmded Operating Conditions" table will define
the conditions for actual device operation.
Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol Parameter DM54S1 " DM14S113 Units
Mln Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current - 1 - 1 mA
IOL Low Level Output Current 20 20 mA
1CLK Clock Frequency (Note 2) 125 80 125 80 MHz
tcLK Clock Frequency (Note 3) 80 60 O 80 60 MHz
tw Pulse Width Clock High
(Note 2) Clock Low 6.5 6.5 ns
Preset Low
tw Pulse Width Clock High
(Note 3) Clock Low ns
Preset Low 1 0 10
tsu Setup Time (Notes 1 a 4) 7 l 7 I ns
tH Input Hold Time (Notes 1 & 4) 0 I O 1 ns
TA Free Air Operating Temperature - 55 125 0 70 T
Not. 1: The symbol tl) indicates the falling edge at the clock pulse is used for reterenoe.
Note 2: th. = 15 pF, Rt. - Mon, TA '= 2S'C and Vcc = 5V.
Not. 3:01. " 50 pF, Ru = Mon, Ts = 25% and Vcc - 5v.
Note 4: TA = 25'C and Voc - 5V.
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note t)
V; InputClamp Voltage Vcc = Min, l, = - 18 mA -1.2 V
VOH High Level Output Vcc = Min, lore = Max DM54 2.5 3.4
Voltage " = Max, VIH = Min DM74 2.7 3.4
VOL Low Level Output Vcc = Min, IOL = Max 0 5 V
Voltage VIH = Min, Vit. = Max .
I. Input Current q Max Vcc = Max, V. = 5.5V
lnputVoltage
IIH High Level Input Vcc = Max J, K 50
Current V. = 2.7V Preset 100 p A
Clock 100
lit. Low Level Input Vcc = Max J, K -1.6
Current VI = 0.5V Preset -7 m A
Clock -4
los Short Circuit Vcc = Max DM54 -40 - 100 m A
Output Current (Note 2) DM74 - 40 _ 100
'00 Supply Current Voc = Max, (Note 3) 30 50 mA
Noto t: All typical: are at Vcc = w, TA = 25'0.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open, lac is measured with the Q and t5 outputs high in turn. At the time of measurement, the clock input is grounded.
Switching Characteristics at Vcc == 5V and TA = 25'C (See Section1 for Test Waveforms and Output Load)
From (Input) “L --- Mon
Symbol Parameter To (Output) th. = " pF th. = 50 pF Unlta
Mln Max Min Max
fMAx Maximum Clock 80 60 MHz
Frequency
tpLH Propagation Delay Time Preset 7 9 ns
Low to High Level Output to Q
tpHL Propagation Delay Time Preset 7 12 n 3
High to Low Level Output to a
tpLH Propagation Delay Time Clock to 7 9 ns
Low to High Level Output Q or Ci
(pm Propagation Delay Time Clock to 7 12 n s
High to Low Level Output 0 or 5
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM74S113N - product/dm74s113n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM54S113J - product/dm54s113j?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
