DM74S112N , Dual Negative-Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsNational _
Semiconductor
DM54S112/DM74S112 Dual Negative-Edge-Triggered
Master-Slave J-K FIip- ..
DM74S113N ,7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset and complementary outputGeneral Description
This device contains two independent negative-edge-trig- negative going edge ..
DM74S11N ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic AND ..
DM74S132N ,Quad 2-Input Schmitt Trigger NAND GateGeneral Description
This device contains four independent gates that perform
the logic NAND fun ..
DM74S133M ,13-Input NAND GateGeneral Description
This device contains a single gate which performs the logic
NAND function.
..
DM74S133MX , 13-Input NAND GateGeneral DescriptionThis device contains a single gate which performs the logicNAND function. Orderi ..
DS2437 ,Smart Battery Monitorblock diagram of Figure 1 shows the seven major components of the DS2437:1. 64-bit lasered ROM2. te ..
DS2438 ,Smart Battery MonitorFEATURES PIN ASSIGNMENT ® Unique 1-Wire interface requires only one port pin for communication ..
DS2438AZ ,Smart Battery MonitorFEATURES PIN ASSIGNMENT ® Unique 1-Wire interface requires only one port pin for communication ..
DS2438AZ+ ,Smart Battery MonitorApplications include portable computers, NC - No connect portable/cellular phones, consumer elect ..
DS2438Z ,Smart Battery MonitorFEATURES PIN ASSIGNMENT® Unique 1-Wire interface requires only oneport pin for communication GND ..
DS2438Z ,Smart Battery MonitorApplications include portable computers,VDD - Power Supply (2.4V to 10.0V)portable/cellular phones, ..
DM74S112N
7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output
National .
Semiconductor
DM54S112/DM74S112 Dual Negative-Edge-Trigger)
Master-Slave J-K FIip-Flops with Preset,
Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse, The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and K
inputs can be changed while the clock is high or low without
affecting the outputs as long as setup and hold times are
not violated. A low logic level on the preset or clear inputs
will set or reset the outputs regardless of the logic levels of
the other inputs.
Connection Diagram
Dual-in-Une Package
Vm: CLRI CLR2 Ctkt
115 I15 " 13
" " PR 2 ttt
li? II I") ,
I 2 3 4
Crkt Kt J1 PR1
5 s 1 s
m tit 62 mm
TLtF/6459-t
Order Number DM54S112J or DM748112N
See NS Package Number J16A or N165
Function Table
Inputs
IIIIIt—Ir'
IIIIIl—I—I
I(—(—(—(—><)<><
Outputs
J K o ti
X X H L
X X L H
X X H . H .
L L 00 Th
H L H L
L H L H
H H Toggle
X X Co CK
H = High Logic Level
= Either Low or High Logic Level
L = Low Logic Level
l -- Negative going edge of pulse.
00 = The output logic level of a before the indicated input conditions were
established.
. = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (high) level.
Toggle = Each output changes to the complement of its previous Level on
each felting edge of the dock pulse.
Absolute Maximum Ratings (Note)
If Mllltary/Aerospace apeclfled devlces are required,
please contacl the National Semiconductor Sales
t9tmtttfDlatrIbutortt for availability and ttpettlfleatlorta.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54S - 55''C to + 125°C
DM74S 0°C to + 70°C
Storage Temperature Range - 65°C to + 15ty'C
Note: The ''Abstguttt Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not he operated at these limits. The
paramstritt values defined in the "Elsotn‘ca/ Characteristics''
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions " table will define
the conditions for actual device operation.
Recommended Operating Conditions (See Section 1 for Test Waveforms and Output Load)
Symbol Parameter DM54S1 " DM74511 2 Unlts
Mln Nom Max Min Nam Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
ViH High Level InputVoltage 2 2 V
VIL Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current -1 -1 mA
IOL Low Level Output Current 20 20 mA
fCLK Clock Frequency (Note 2) 0 125 80 0 125 80 MHz
1cm Clock Frequency (Note 3) 80 60 0 80 60 MHz
tw Pulse Width Clock High 6 6
(Note 2) Clock Low 6.5 6.5 ns
Clear Low 8 8
Preset Low 8 8
tw Pulse Width Clock High 8 8
(Note 3) Clock Low 8 8 ns
Clear Low 10 10
Preset Low 10 10
tsu Setup Time (Notes 1 8. 4) 7 l 7 l ns
tH Input Hold Time (Notes 1 & 4) 0 l 0 I ns
TA Free Air Operating Temperature - 55 125 0 70 "C
Note t: The symbol (l) indicates the falling edge at the clock pulse is used for reference.
Note 2:61. " 15 pF, Rt. = 280n, TA = 25'C and Vct; = 5V.
"m 3.. CL = 50 PF. HI. = 2800. TA = 25'C and VOC = SV.
Note 4: TA = 25°C and Vcc = 5V.
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 1)
V] Input Clamp Voltage Vcc = Min, II = - 18 mA - 1.2 V
VOH High Level Output VCC = Min, ioH = Max DM54 2.5 3.4
Volta e V = Max V = Min V
g IL , IH DM74 2.7 3.4
VOL Low Level Output Vcc = Min, IOL = Max
Voltage VIH = Min, " = Max 0.5 V
II InputCurrent @ Max Vcc = Max, V. = 5.5V
Input Voltage
‘lH High Level Input Vcc = Max J, K 50
Current V. = 2.7V Clear 100
Preset 100
Clock 100
IIL Low Level Input Vcc = Max J, K -1.6
Current v, = 0.5V Clear -7
(Note 4) Preset - 7
Clock -4
las Short Circuit Vcc = Max DM54 -40 -100
Output Current (Note 2) DM74 - 40 - 100
Ice Supply Current Vcc = Max (Note 3) 30 50 mA
Note 1: All typicals are at Vcc "--. 5V, TA -- 25'C.
Note 2: Not more than one output should be shorted at a time, and the duration shouid not exceed one second.
Note 3: With all outputs open, log is measured with the Q and G outputs high in turn. At the time of measursment. the dock input is grounded.
Nola 4: Gear is tested with preset high and preset is tested with clear high.
Switching Characteristics at Vcc = 5V and TA = 25''C (See Section 1 for TestWaveforms and Output Load)
RL = 2800
From (Input)
Symbol Parameter To (Output) th. = 15 pF A. = so pF Units
Min Max Min Max
fMAx Maximum Clock
Frequency 80 60 MHz
tpLH Propagation Delay Time Preset 7 9 ns
Low to High Level Output to Q
tPHL Propagation Delay Time Preset 7 12 ns
High to Low Level Output to 5
tpLH Propagation Delay Time Clear 7 9 ns
Low to High Level Output to G
tpHL Propagation Delay Time Clear 7 12 ns
High to Low Level Output to Q
tpLH Propagation Delay Time Clock to 7 9 ns
Low to High Level Output 0 or G
tPHL Propagation Delay Time Clock to 7 12 n s
High to Low Level Output Q or G
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM74S112N - product/dm74s112n?HQS=T|-null-nulI-dscatalog-df-pf-null-wwe
DM54S112J - product/dm54s112j?HQS=T|-nulI-nulI-dscatalog-df—pf—nuII-wwe
