DM74S02N ,Quad 2-Input NOR GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NOR ..
DM74S04M ,Hex Inverting GatesGeneral DescriptionThis device contains six independent gates each of whichperforms the logic INVER ..
DM74S05M ,Hex Inverter with Open-Collector OutputsDM74S05 Hex Inverter with Open-Collector OutputsAugust 1986Revised April 2000DM74S05Hex Inverter wi ..
DM74S05N ,Hex Inverter with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM74S08N ,Quad 2-Input AND GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic AND ..
DM74S09N ,Quad 2-Input AND Gates with Open-Collector OutputsDM74S09Quad2-InputANDGateswithOpen-CollectorOutputsJune1989DM74S09Quad2-InputANDGateswithOpen-Colle ..
DS2433X ,4 kbit 1-Wire EEPROMPIN DESCRIPTION§ 8-bit family code specifies DS2433PR-35 SOICcommunication requirements to readerPi ..
DS2433X#U ,4Kb 1-Wire EEPROMPIN DESCRIPTION 8-bit family code specifies DS2433PR-35 SOcommunication requirements to readerPin ..
DS2433X-S#T ,4Kb 1-Wire EEPROMFEATURES 4096 bits Electrically Erasable ProgrammableRead-Only Memory (EEPROM)PR-35 Unique, facto ..
DS2434 ,Battery identification chipPIN DESCRIPTIONPIN PIN14-PIN SOIC PR35 SYMBOL DESCRIPTION1 1 GND Ground pin14 2 DQ Data Input/Outpu ..
DS2435 ,Battery identification chip with time/temperature histogramPIN DESCRIPTIONPIN PIN16-PIN SSOP PR-35 SYMBOL DESCRIPTION8, 9 1 GNDGround pin.12 DQ Data Input/Out ..
DS2435 ,Battery identification chip with time/temperature histogramPIN DESCRIPTIONGND - GroundDQ - Data In/OutV - Supply VoltageDDNC - No ConnectDESCRIPTIONThe DS2435 ..
DM74S02N
Quad 2-Input NOR Gate
DM74S02 Quad 2-Input NOR Gate August 1986 Revised May 2000 DM74S02 Quad 2-Input NOR Gate General Description This device contains four independent gates each of which performs the logic NOR function. Ordering Code: Order Number Package Number Package Description DM74S02N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Y = A + B Inputs Output AB Y LL H LH L HL L HH L H = HIGH Logic Level L = LOW Logic Level © 2000 DS006490
