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DM74LS962N-DM86LS62N
Dual Rank 8-Bit TRI-STATE Shift Register
TL/F/6438
DM74LS962
(DM86LS62)
Dual
Rank
8-Bit
TRI-STATE
Shift
Register
August 1991
DM74LS962 (DM86LS62)
Dual Rank 8-Bit TRI-STATEÉ Shift Register
General Description
Thesecircuitsare TRI-STATE, edge-triggered, 8-bitI/Oreg-
istersin parallel with 8-bit serial shift registers whichare
capableof operatinginanyofthe following modes: parallel
load fromI/O pinsto register ‘‘A’’, parallel transfer down
from register‘‘A’’to serialshiftregister ‘‘B’’, parallel transfer fromshift register‘‘B’’to register ‘‘A’’, serial shiftof regis-
ter ‘‘B’’,or exchange data between register ‘‘A’’and shift
register ‘‘B’’. Sincethe registersare edge-triggeredbythe
positive transitionofthe clock,the control lines which deter-
minethe modeor operationare completely independentof
the logic level appliedtothe clock. Designedfor bus-orient- systems, these circuits have their TRI-STATE inputsand
outputsonthe same pins.
Features Registersare edge-triggeredbythe positive transitionthe clockAll inputsare PNP transistors Input disable dominates over output disable Output high impedance state doesnot impedeany oth- modeof operation 8-bitI/O pinsare TRI-STATE buffers Typical shift frequencyis36 MHz Typical power dissipationis305 mWAll control inputsare active wheninan‘‘L’’ logic state Devicescanbe cascadedinto N-bit word
Connection Diagram
Dual-In-LinePackage
TL/F/6438–1
Top View
Order Number DM74LS962Nor DM86LS62N
See NSPackage Number N18A
Pin Description
DISOÐOutput disable
ISÐSerial input
DISIÐInput disable
DISTUÐTransferup disable
DISTDÐTransfer down disable
DISSÐShift disable
OSÐSerial output
CLKÐClock
GNDÐGround
I/O1...I/O 8Ð8-bitI/O pins
VCCÐSupply Voltage
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
