DM74LS952N ,7 V, dual rank 8-bit TRI-STATE shift registerFeatures
I Registers are edge-triggered by the positive transition
of the clock
I All inputs ..
DM74LS962N ,Dual Rank 8-Bit TRI-STATE Shift RegisterFeaturesYRegisters are edge-triggered by the positive transitionThesecircuitsareTRI-STATE,edge-trig ..
DM74S00 ,Quad 2-Input NAND GateDM54S00/DM74S00Quad2-InputNANDGatesJune1989DM54S00/DM74S00Quad2-InputNANDGatesGeneralDescriptionThi ..
DM74S00N ,Quad 2-Input NAND GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND ..
DM74S02N ,Quad 2-Input NOR GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NOR ..
DM74S04M ,Hex Inverting GatesGeneral DescriptionThis device contains six independent gates each of whichperforms the logic INVER ..
DS2433+ ,4Kb 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2433S ,4 kbit 1-Wire EEPROMFEATURES PIN ASSIGNMENT§ 4096 bits Electrically Erasable ProgrammableNC 1 8 NCRead Only Memory (EEP ..
DS2433X ,4 kbit 1-Wire EEPROMPIN DESCRIPTION§ 8-bit family code specifies DS2433PR-35 SOICcommunication requirements to readerPi ..
DS2433X#U ,4Kb 1-Wire EEPROMPIN DESCRIPTION 8-bit family code specifies DS2433PR-35 SOcommunication requirements to readerPin ..
DS2433X-S#T ,4Kb 1-Wire EEPROMFEATURES 4096 bits Electrically Erasable ProgrammableRead-Only Memory (EEPROM)PR-35 Unique, facto ..
DS2434 ,Battery identification chipPIN DESCRIPTIONPIN PIN14-PIN SOIC PR35 SYMBOL DESCRIPTION1 1 GND Ground pin14 2 DQ Data Input/Outpu ..
DM74LS952N
7 V, dual rank 8-bit TRI-STATE shift register
National
1 Semiconductor
DM74LS952
Dual Rank 8-Bit TRl-STATE® Shift Registers
General Description
These circuits are TRI-STATE, edge-triggered, 8-bit " reg-
isters in parallel with B-bit serial shift registers which are
capable of operating in any of the following modes: parallel
load from IIO pins to register "A", parallel transfer down
from register "A" to serial shift register "B", parallel transfer
up from shift register "B" to register "A", serial shift of regis-
ter "B", synchronously clear. Since the registers are edge-
triggered by the positive transition of the clock, the control
lines which determine the mode or operation are completely
independent of the logic level applied to the clock. De-
signed tor bus-oriented systems, these circuits have their
TRI-STATE inputs and outputs on the same pins.
Features
a Registers are edge-triggered by the positive transition
of the clock
I: All inputs are PNP transistors
:1 Input disable dominates over output disable
a Output high impedance state does not impede any oth..
er mode of operation
a 8-bit I/O pins are TRl-STATE buffers
II Typical shift frequency is 36 MHz
" Typical power dissipation is 305 mW
D All control inputs are active when in an "L'' logic state
I: Devices can be cascaded into N-bit word
Connection Diagram
DuaMrt-Lirte Package
Vcc 1/01 1/02 1/03 1/04 vos I/06 1/07 1/08
Pln Descriptlon
" " " " " " 12 11 " DlSo-Output disable
ls-Serial input
DlSr--lnput disable
I DSW-Transfer up disable
--1 1/0 BUFFERS 'r- DISrtr-Transftsr down disable
0 DISs-Shift disable
CONTROL Os-Serial output
LOGIC ---l UPPER REG "A CLK-ttlock
U TRANSFER M " GND-Ground
-H LOWER SHIFT REG "B" I/O 1 ... I/O 8-8-bit IIO pins
" I Vcc-Supply Voltage
___._I I
1 2 3 4 5 a r 8 I'
Disc Is DIS] NSTU 01510 DlSs os CLK GND
TL/F/6437-1
Top View
Order Number DM74LS952N
See NS Package Number N1BA
3968']
Absolute Maximum Ratings (Note)
If MllitaryfAerospatte trpeelfled devices are required,
please contact the National Semiconductor Sales
Offlee/Dlstrlhutora for avallablllty and ttpet0ttatlurta.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM74LS C'C to + 7tr'C
Storage Temperature Range -65''C to + 150''C
Lead Temperature (Soldering, 10 seconds) 300°C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of (he device cannot be guaran-
teed. The de vice should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Rettomrmmdttd Operating Conditions" table will define
the conditions far actual device operation.
Symbol Parameter DM74LS952 Units
Min Typ Max
Vcc Supply Voltage 4.75 5 5.25 V
VIH High-Level Input Voltage 2 V
" Low-Level Input Voltage 0.8 V
IOH High-Level Output Current _ 5.2 mA
IOL Low-Level Output Current 16 mA
fCLOCK Clock Frequency (Note 5) 0 25 MHz
Clock Pulse High Pulse Width (Note 5) 25 17 ns
Low Pulse Width (Note 5) 15 7 ns
tSET.Up Data Set-Up Time (Note 5) 10 ns
tHOLD Data Hold Time (Note 5) 0 ns
TA Free Air Operating Temperature 70 "C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Condlllons (1) DMNLS952 Unlls
Mln Typ (2) Max
V. Input Clamp Voltage VCC = Min, ll = -18 mA - 1.5 V
VOH High-Level OutputVoltage Vcc = Min, VIH = 2V, IOH = -5.2 mA
Vm=VmMa
VOL Low-Level OutputVoltage Vcc = Min, 1/iH = iN, IOL = 8 mA 0.25 0.4 V
WL=VKM” bL=16mA 0.35 as
I. Input Current at Maximum Vcc = Max, VI = 5.5V
0.1 mA
Input Voltage
IIH High-Level Input Current Vcc = Max, V. = 2.7V 20 MA
||L Low-Level InputCurrent Vcc = Max, VI = 0.4V --50 pA
los Short-Circuit Output Current Voc = Max (3) -20 - 100 mA
ICC Supply Current V00 = Max (4) 61 99 mA
lop; TRI-STATE l/O Current Vcc = Max, VIH = 2V vo = 2.4V 20 p.A
V0 = 0.4V -20 0A
Note 1: For conditions shown as min or max, use me appropriate value specified under recommended operating conditions.
Note 2: All typical values are at VCC = 5V. TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Note 4: Ice is measured with serial output open. the clock and shift disable input at 2.4V. Ali other control inputs and MO pins grounded.
Note tit TA = 25°C and Vcc = 5V.
Switching Characteristics at Vcc = 5V and TA = 25°C (See Section 1 forTestWaveforms and Output Load)
Symbol Parameter Conditions Min Max Units
fMAx Maximum Clock Frequency 25 MHz
tpLH Propagation Delay Time, Low-to-High-Level 7 33 ns
from Clock to Any Outputs
tpHL Propagation Delay Time, High-to-Low Level 1 0 48 ns
from Clock to Any Output tk = 15 pF, RL = 1 kn.
tENABLE Enable Time trom Any Control Inputs 5 24 ns
IDISABLE Disable Time from Any Control Inputs 6 27 ns
tPZH Output Enable Time to High Level 5 23 ns
thL Output Enable to Low Level 4 18 ns
tsz Output Disable Time from High Level CL = 5 pF, RL = 1 k n 5 23 ns
tPLZ Output Disable Time from Low Level 6 27 ns
Logic Diagram
I/O 1 vo 2
. . I OBITS
os CLOCK
TL/F16437-2
Function Table
Table I
fl-Blt HQ
0150 ms. ms“, msm mss CLK Pm
Content 0! Upper Reg. "A"
Content of Lower Serlal Shift Reg. "B"
Comments
Output
Stable state
Entering data from |/0 to reg. "A"
Output
<—<—-<——DOR—>—>—>
v-v-I-
Transfer data up from reg. “B" to reg. “A"
Reg. “A" will OR data trom |/O to reg. ”B"
Output
I-v-V'
Transfer data down from reg. “A” to reg. “B"
Entering data and transfer down
Output
(1) Synchronously clear both registers to
(2) togic "L” level
(3) Enter data to reg. “A" clear reg. “B"
Output
Serial shifting in the lower reg. “B"
Entering data and serial shifting
Output
xxx xxx xxx xxx 1:01: 1:131:
Ayt4- F-F-4- t-4-e- 4-4-4- 6-6-4- 6-4-e.
III III xxx xxx .14.: .14.:
xxx III 4.1.: ..d-l-l III III
TTCE-l-l-dx'::...:-:-:::':.:-:-'-'
xx-g CET-l 11.: II-I 11.: 11.:
<—<—<—DOR—>—>-+
-t-u-JTgTTT3TyTyTy
Transfer up and serial shifting
DOR function and serial shifting
T-IM 1.1x 1.1x 14x x_xx x_ux "
Don’t Care
HPZ/Omnut/Inam/ E High impedance stateloutput state/input state
at . . . a8/b1 . . . b8 5 “19 content of the upper register “A"lthe lower serial shift register “8“ before the most recent T transition ot the clock
I. . .. I9 2 The level of steady state inputs at the I/O pins
DOR 5 ”Data ORing function" ORing data from both l/O pins and register “B", La. I1 + b1, 12 + b2. l3 + be . . . '5 + b8
(12 Datacfthesetialinpm
Timing Diagram
CONTENT OF LOWER SERIAL
SHFT REGISTER
DM54/74LS952
BEFORE I/O , o . . I/O tt
PULSE tt o: 01 01 01
UPPER REG "A"
Is LOWER SHFT REG "Br os
0 0 o O
rttFSTATE
Ot , 01 O1
01 0 '" Ot
TL/F/6437-3
ZSGS'I
AC Test Circuit and Switching Time Waveforms
TEST POINY
FROM OUTPUT
UNDER TE ST
HIGH CLOCK
M diodes are 1N916 or 1N3064.
CL includes probe and jig capacitance.
TL/F/6437-4
PULSE WIDTH - h -
cm 1.3V
ov y, A
'd.'llifli"fe- - 'ENABLE - tmsattcE
tSt 3v
D . MSTU
ms“, & ms; 1.3V
tSET-UP +I _ - ‘de
31t - _
l/OL ls 1.3V /V
- 'HOLD * - trtc
o,5v o.5v VOH - _L. / Von
vo i 1 I '/oa0s 1.3v------ 1
VOL ----'-F 'ci-, D.SY o.sv VOL o-.--,
DlSo Lav
tLa - - s---ta - tHg _ le <-
TLfF/643r-6
All input pulses are supplied by generators having k s 15 ns, t, s 6 ns, PRR s 1 MHz, ZOUT Ar. 50n.
Cascading Packages
Cascading Packages tor N-Bit Word
l/O1 - . . l/OB I/O1 I . c I/OB . o . Nl/OHNS
DMMLSB52 DMSM.5952
Is Os ts Os
DISTU -
0510 -
DISs -
TL/F/6437-6
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM74LS952N - product/dm74lsQ52n?HQS=TI-nu|I-nu|l-dscataIog-df-pf-null-wwe
