DM74LS90N ,Decade and Binary CountersFeaturesEach of these monolithic counters contains four master- Typical power dissipation 45 mWsla ..
DM74LS93N ,Decade and Binary CountersFeaturesYTypical power dissipation 45 mWTo use their maximum count length (decade or four bit bina- ..
DM74LS952N ,7 V, dual rank 8-bit TRI-STATE shift registerFeatures
I Registers are edge-triggered by the positive transition
of the clock
I All inputs ..
DM74LS962N ,Dual Rank 8-Bit TRI-STATE Shift RegisterFeaturesYRegisters are edge-triggered by the positive transitionThesecircuitsareTRI-STATE,edge-trig ..
DM74S00 ,Quad 2-Input NAND GateDM54S00/DM74S00Quad2-InputNANDGatesJune1989DM54S00/DM74S00Quad2-InputNANDGatesGeneralDescriptionThi ..
DM74S00N ,Quad 2-Input NAND GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND ..
DS2431X-S+ ,1024-Bit 1-Wire EEPROMGeneral Description Beneits and
DS2432 ,1kb Protected 1-Wire EEPROM with SHA-1 Engineblock diagram in Figure 1 shows the relationships between the major control and memory sections of ..
DS2432 ,1kb Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN CONFIGURATIONS 1128 Bits of 5V EEPROM Memory TOP VIEW Partitioned Into Four Pages ..
DS2432P ,1k-Bit Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN ASSIGNMENT 1128 bits of 5V EEPROM memory parti-tioned into four pages of 256 bits, a ..
DS2432P-W01+4T ,1Kb Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN CONFIGURATIONS 1128 Bits of 5V EEPROM Memory TOP VIEW Partitioned Into Four Pages ..
DS2433 ,4 kbit 1-Wire EEPROMPIN DESCRIPTION 8-bit family code specifies DS2433PR-35 SOcommunication requirements to readerPin ..
DM74LS90N
Decade and Binary Counters
DM74LS90 Decade and Binary Counters August 1986 Revised March 2000 DM74LS90 Decade and Binary Counters General Description Features Each of these monolithic counters contains four master- � Typical power dissipation 45 mW slave flip-flops and additional gating to provide a divide-by- � Count frequency 42 MHz two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the Q output. The A input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetri- cal divide-by-ten count can be obtained from the DM74LS90 counters by connecting the Q output to the A D input and applying the input count to the B input which gives a divide-by-ten square wave at output Q . A Ordering Code: Order Number Package Number Package Description DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Reset/Count Truth Table Reset Inputs Output R0(1) R0(2) R9(1) R9(2) Q Q Q Q D C B A H H L X LLLL H H X L LLLL XX H H H L L H X L X L COUNT L X L X COUNT L X X L COUNT X L L X COUNT © 2000 DS006381
