DM74LS90N ,Decade and Binary CountersFeaturesEach of these monolithic counters contains four master- Typical power dissipation 45 mWsla ..
DM74LS93N ,Decade and Binary CountersFeaturesYTypical power dissipation 45 mWTo use their maximum count length (decade or four bit bina- ..
DM74LS952N ,7 V, dual rank 8-bit TRI-STATE shift registerFeatures
I Registers are edge-triggered by the positive transition
of the clock
I All inputs ..
DM74LS962N ,Dual Rank 8-Bit TRI-STATE Shift RegisterFeaturesYRegisters are edge-triggered by the positive transitionThesecircuitsareTRI-STATE,edge-trig ..
DM74S00 ,Quad 2-Input NAND GateDM54S00/DM74S00Quad2-InputNANDGatesJune1989DM54S00/DM74S00Quad2-InputNANDGatesGeneralDescriptionThi ..
DM74S00N ,Quad 2-Input NAND GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND ..
DS2431X-S+ ,1024-Bit 1-Wire EEPROMGeneral Description Beneits and
DS2432 ,1kb Protected 1-Wire EEPROM with SHA-1 Engineblock diagram in Figure 1 shows the relationships between the major control and memory sections of ..
DS2432 ,1kb Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN CONFIGURATIONS 1128 Bits of 5V EEPROM Memory TOP VIEW Partitioned Into Four Pages ..
DS2432P ,1k-Bit Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN ASSIGNMENT 1128 bits of 5V EEPROM memory parti-tioned into four pages of 256 bits, a ..
DS2432P-W01+4T ,1Kb Protected 1-Wire EEPROM with SHA-1 EngineFEATURES PIN CONFIGURATIONS 1128 Bits of 5V EEPROM Memory TOP VIEW Partitioned Into Four Pages ..
DS2433 ,4 kbit 1-Wire EEPROMPIN DESCRIPTION 8-bit family code specifies DS2433PR-35 SOcommunication requirements to readerPin ..
DM74LS90N-DM74LS93N
Decade and Binary Counters
TL/F/6381
DM74LS90/DM74LS93
Decade
and
Binary
Counters
June 1989
DM74LS90/DM74LS93
Decade and Binary Counters
General Description
Eachof these monolithic counters contains four master-
slave flip-flopsand additional gatingto providea divide-by-
two counteranda three-stage binary counterfor whichthe
count cycle lengthis divide-by-fiveforthe ’LS90and divide-
by-eightforthe ’LS93.
Allof these counters havea gated zero resetandthe LS90
alsohas gatedset-to-nineinputsforusein BCD nine’s com-
plement applications.use their maximum count length (decadeorfourbit bina-
ry),theB inputis connectedtotheQA output. The input
count pulsesare appliedto inputAandthe outputsareas
describedinthe appropriate truth table.A symmetricaldi-
vide-by-ten countcanbe obtained fromthe ’LS90 counters connectingtheQD outputtotheA inputand applyingthe
inputcount totheB input which givesa divide-by-ten square
waveat outputQA.
Features Typical power dissipation45 mW Count frequency42 MHz
Connection Diagrams (Dual-In-LinePackages)
TL/F/6381–1
OrderNumberDM74LS90Mor DM74LS90N
SeeNS Package Number M14AorN14A
TL/F/6381–2
Order Number DM74LS93MorDM74LS93N
SeeNS PackageNumberM14Aor N14A
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
