DM74LS85N ,4-Bit Magnitude ComparatorFeaturesThese 4-bit magnitude comparators perform comparison of Typical power dissipation 52 mWstr ..
DM74LS86 ,Quad 2-Input Exclusive-OR GateDM54LS86/DM74LS86Quad2-InputExclusive-ORGatesJune1989DM54LS86/DM74LS86Quad2-InputExclusive-ORGatesG ..
DM74LS86M ,Quad 2-Input Exclusive-OR GateDM54LS86/DM74LS86Quad2-InputExclusive-ORGatesJune1989DM54LS86/DM74LS86Quad2-InputExclusive-ORGatesG ..
DM74LS86M ,Quad 2-Input Exclusive-OR GateGeneral DescriptionThis device contains four independent gates each of whichperforms the logic excl ..
DM74LS86N ,Quad 2-Input Exclusive-OR GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic excl ..
DM74LS90N ,Decade and Binary CountersDM74LS90/DM74LS93DecadeandBinaryCountersJune1989DM74LS90/DM74LS93DecadeandBinaryCountersGeneralDesc ..
DS2431P+ ,1024-Bit 1-Wire EEPROMFeatures®The DS2431 is a 1024-bit, 1-Wire EEPROM chip orga- ● Easily Add Traceability and Relevant ..
DS2431P+T , 1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently
DS2431P+T , 1024-Bit, 1-Wire EEPROM Individual Memory Pages Can Be Permanently
DS2431P+T&R ,1024-Bit 1-Wire EEPROMElectrical Characteristics(T = -40°C to +85°C.) (Note 1)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UN ..
DS2431P+TR , 1024-Bit, 1-Wire EEPROM
DS2431P-A1+T ,1024-Bit 1-Wire EEPROMFeatures®The DS2431 is a 1024-bit, 1-Wire EEPROM chip orga- ● Easily Add Traceability and Relevant ..
DM74LS85N
4-Bit Magnitude Comparator
DM74LS85 4-Bit Magnitude Comparator August 1986 Revised March 2000 DM74LS85 4-Bit Magnitude Comparator General Description Features These 4-bit magnitude comparators perform comparison of � Typical power dissipation 52 mW straight binary or BCD codes. Three fully-decoded deci- � Typical delay (4-bit words) 24 ns sions about two, 4-bit words (A, B) are made and are exter- nally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B out- puts of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least- significant bits must have a high-level voltage applied to the A = B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words. Ordering Code: Order Number Package Number Package Description DM74LS85M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS85N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006379
