DM74LS74AN ,Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered D flip-flops with ..
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DS2430AP ,256 bit 1-Wire EEPROMapplications include storage of calibration constants, board identification and productrevision sta ..
DS2430AP+ ,256-Bit 1-Wire EEPROMFEATURES PIN ASSIGNMENT 256-bit Electrically Erasable ProgrammableTO-92Read Only Memory (EEPROM) p ..
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DS2430AP+T&R ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2430AP+TR , 256-Bit 1-Wire EEPROM
DS2430AP+TR , 256-Bit 1-Wire EEPROM
DM74LS74AM-DM74LS74AN
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-trig- gered D flip-flops with complementary outputs. The infor- mation on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS85ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H L L X X H (Note 1) H (Note 1) HH ↑ HH L HH ↑ LL H HH L X Q Q 0 0 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level ↑ = Positive-going Transition Q = The output logic level of Q before the indicated input conditions were 0 established. Note 1: This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (HIGH) level. © 2000 DS006373
