DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsDM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Out ..
DM74LS74AM ,Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered D flip-flops with ..
DM74LS74AN ,Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered D flip-flops with ..
DM74LS75N ,Quad LatchGeneral DescriptionThese latches are ideally suited for use as temporary stor-age for binary inform ..
DS2415P/T&R ,1-Wire Time ChipPIN DESCRIPTION Built-in multidrop controller ensurescompatibility with other MicroLAN products Pi ..
DS2415P-W ,1-Wire Time Chipfeaturescan be used to add functions such as calendar, time and date stamp, and logbook to any type ..
DS2423P ,4kbit 1-Wire RAM with CounterPIN DESCRIPTIONcompatibility with other MicroLAN productsPin 1 Ground Directly connects to a singl ..
DS2430 ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DS2430A ,256 bit 1-Wire EEPROMFEATURES PIN ASSIGNMENT 256-bit Electrically Erasable ProgrammableTO-92Read Only Memory (EEPROM) p ..
DS2430A ,256 bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DM74LS73AN
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74LS73AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS73AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs CLR CLK J K Q Q LX X X L H H ↓ LL Q Q 0 0 H ↓ HL H L H ↓ LH L H H ↓ H H Toggle HH X X Q Q 0 0 H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↓ = Negative going edge of pulse. Q = The output logic level before the indicated input conditions were 0 established. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. © 2000 DS006372
