DM74LS670N ,3-STATE 4-by-4 Register FileFeatures
I Alternate Military/Aerospace device (54LS670) is avail-
able. Contact a National Sem ..
DM74LS670N ,3-STATE 4-by-4 Register FileGeneral Description
These register tiles are organized as 4 words of 4 bits each,
and separate ..
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DM74LS670N
7 V, TRI-STATE 4-by-4 register file
National
I Semiconductor
54LS6r0/DM54LS670/DM74LS670
TRI-STATE® 4-by-4 Register Files
General Description
These register files are organized as 4 words of 4 bits each,
and separate on-chip decoding is provided for addressing
the four word locations to either write-in or retrieve data.
This permits writing into one location, and reading from an-
other word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write se-
lect inputs A and B, in conjunction with a write-enable sig-
nal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data will
be accepted only if both internal address gate inputs are
high. When this condition exists, data at the D input is trans-
ferred to the latch output. When the write-enable input, Gw,
is high, the data inputs are inhibited and their levels can
cause no change in the information stored in the internal
latches. When the read-enable input, GR, is high, the data
outputs are inhibited and go into the high impedance state.
The individual address lines permit direct acquisition of data
stored in any tour of the latches. Four individual decoding
gates are used to complete the address for reading a word.
When the read address is made in conjunction with the
read-enabte signal, the word appears at the four outputs.
This arrangement-data entry addressing separate from
data read addressing and individual sense line - eliminates
recovery times, permits simultaneous reading and writing,
and is limited in speed only by the write time (27 ns typical)
and the read time (24 ns typical). The register file has a non-
volatile readout in that data is not lost when addressed.
All inputs (except read enable and write enable) are butt-
ered to lower the drive requirements to one normal Series
54LS/74LS load, and input clamping diodes minimize
switching transients to simplify system design. High speed.
double ended AN D-OR-PII/ERT gates are employed for the
read-address function and have high sink current, TRI-
STATE outputs. Up to 128 of these outputs may be wire-
AND connected for increasing the capacity up to 512 words.
Any number of these registers may be paralleled to provide
n-bit word length.
Features
I: Alternate Military/Aerospace device (54LS670) is avail-
able. Contact a National Semiconductor Sales Office/
Distributor tor specifications.
n For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
a Separate read/write addressing permits simultaneous
reading and writing
a Organized as 4 words of 4 bits
n Expandable to 512 words of n-bits
II TRI-STATE versions of DM54LS170/DM74LS170
n Fast access times 20 ns typ
Connection Diagram
Dual-ln-Line Package
DATA WRITE SELECT ENABLE OUTPUTS
INPUT - ,__
Vcc '" WA W3 Gw Ga 01 02
" " " "Italo
|123t557la
tuttBrtatMt23GNtt
u..------" _---. _-r-.'
DATA READ OUTPUTS
INPUTS SELECT
TUF/6436-1
Order Number 54L5670DMQB, 54LS6r0FMt2B,
54LS670LMQB, DMS4LS670d, DM54L5670W,
DM74L5670M or DM74LSG7ON
See NS Package Number EMA,
J16A, M16A, N16A or W16A
Function Tables
WRITE TABLE (SEE NOTES A, B, AND C)
Write Inputs Word
W3 WA Gw o 1 2 3
L L L Q = D 00 Go 00
L H L th Q = D 00 00
H L L th 00 Q = D th
H H L Go 00 00 Q = D
X X H Go Co 00 00
READ TABLE (SEE NOTES A AND D)
Read Inputs Outputs
Ha HA Ga 01 02 Q3 04
L L L WOBI WOB2 WOB3 W054
L H L W181 WIB2 W183 W184
H L L W281 W252 W283 W284
H H L W381 W332 W333 W3 B4
X X H Z Z Z Z
Note A: H = High Level. L = Low Level, X = Don't Care, 2 -- High
impedance (Off).
Note B.. (Q = D) = The tour selected tntemal frrtsikm outputs will assume
the states applied to the tour external data inputs.
Note c: th --- The level ot Q before the indicated input conditions were
established.
Note D: WOBt = The first bit of ward o, etc.
Absolute Maximum Ratings (Note)
If MllltaryfAerotrpatre specified devlces are required,
please contact the National Semiconductor Sales
offleefDhttrlbutors for availability and specifications.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
DM54LS and 54LS --55''C to + 125°C
DM74LS ty'C to + 70°C
Storage Temperature Range -65''C to + 150''C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The de vice should not be operated at these limits. The
parametric values defined in the "Electrical Charmrtatistios''
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.
Symbol Parameter DMMLSGTO DM74LSt00 Units
Mln Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
Vm High Level Input Voltage 2 2 V
Ihr. Low Level Input Voltage 0.7 0.8 V
10H High Level Output Current - 1 - 2.6 mA
IOL Low Level Output Current 12 24 mA
tw Write Enable Pulse Width
(Note 3) 25 25 ns
tsu Setup Time Data 1 0 10
Notes 1 & 3) ns
( WA, we 15 15
1.4 Hold Time Data 15 15 ns
(Notes 1 & 3) WA, W3 5 5
tLATCH Latch Time for New Data
(Notes 2 a a) 25 25 ns
TA Free Air Operating - 55 125 0 70 "C
Temperature
Note 1: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. It protection of data in the
previous address, [SETUP (WA. W3) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tA (WA. We) will
Iesult in data being written into that location. Depending on the duration of the input conditions. one or a number of previous addresses may have been written into.
Note 2: Latch time is the time allowed tor the internal output of the latch to assume the state of new data. This is inponant only when attempting to read from a
location immediately after that location has received new data.
Hole P. TA = 25°C and Voc = 5V.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min ("351) Max Units
V. InputClamp Voltage Vcc = Min, 1. = -18 mA -1.5 V
VOH High Level Output Voltage Vcc = Min, IOH = Max 2.4 3.4 V
" == Max,le = Min
VOL Low Level OutputVoltage Vcc = Min, lor. = Max DM54 0.25 0.4 V
lot. = Max, VIH = Min DM74 0.34 0.5
k Input Current @ Max Vcc = Max D, R or W 0.1
lnputVoltagts VI = 7V GW 0.2 m A
Ga 0.3
ltH High Level Input Current Vcc = Max D, R or W 20
v. = 2.7V Gw 40 ”A
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) (Continued)
Symbol Parameter Conditions Min (Note 1) Max Unlts
IIL Low Level lnputCurrent Vcc = Max D, R, orW -0.4
V' = 0.4V Gw -0.8 mA
Gn - 1 .2
IOZH Ott-State Output Current Vcc = Max,Vo = 2.7V
with High Level Output VIH = Min, " = Max 20 "A
Voltage Applied
IOZL Off-State Output Current Vcc = Max, vo = 0.4V
with Low Level Output Vm = Min, VI. = Max -20 pA
Voltage Applied
los Short Circuit Vcc = Max DM54 -20 -100
Output Current (Note 2) mA
DM74 -20 - 100
'00 Supply Current V00 = Max (Note 3) 30 50 mA
Switching Characteristics at Vcc == 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
RL = 667n
Symbol Parameter From (input) CL = 45 pF A. = 150 pF Units
To (Output)
Mln Max Min Max
tpLH Propagation Delay Time Read Select 40 50 ns
Low to High Level Output to t2
tPHL Propagation Delay Time Read Select 45 55 ns
High to Low Level Output to t2
mm Propagation Delay Time Write Enable 45 55 ns
Low to High Level Output to Q
tPHL Propagation Delay Time Write Enable 50 60 ns
High to Low Level Output to Q
tpLH Propagation Delay Time Data 45 55 ns
Low to High Level Output to Q
tpHL Propagation Delay Time Data 40 50 ns
High to Low Level Output to Q
tPZH Output Enable Time Read Enable 35 45 ns
to High Level Output to Any 0
tPZL Output Enable Time Read Enable
to Low Level Output to Any a 40 50 ns
tsz Output Disable Time from Read Enable 50 ns
High Level Output (Note 4) to Any 0
tPLZ Output Disable Time from Read Enable 35 ns
Low Level Output (Note 4) to Any t2
Note I: All typicals are at Voc --- 5V, TA = 25°C.
Note 2: Not mote than one output should be shoned at a time, and the duration should not exceed one second.
Note 3: ICC is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are open.
Note 4: Ct = 5 pF.
0193']
Logic Diagram
ourpu‘rs
113) (14) m (11) ts)
Gw W3 WA an on "
_------. _-.---..---
mm READ INPUT
TL/F/6436-2
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
DM54LS670W - product/dm54lsG70w?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuIl-wwe
DM74LS670M - product/dm74lsG70m?HQS=T|-nu|I-nu|I-dscataIog-df-pf-null-wwe
DM74LS670N - product/dm74lsG70n?HQS=T|—nu|I-nu|I-dscataIog-df-pf-null-wwe
54LS670LMQB - product/54IsS7OImqb?HQS=TI—nu|I—nu|I-dscatalog-df-pf—null-wwe
DM54LS670J - product/dm54|s670j?HQS=T|-null-nuII-dscatalog-df-pf—nuII-wwe
54LS670DMQB - product/54ls670qub?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
54LS670FMQB - product/54IsS70fmqb?HQS=T|-null-null-dscatalog-df—pf—nuII-wwe
