DM74LS670MX , 3-STATE 4-by-4 Register FileGeneral Descriptionwriting, and is limited in speed only by the write time (27 nsThese register fil ..
DM74LS670N ,3-STATE 4-by-4 Register FileFeatures
I Alternate Military/Aerospace device (54LS670) is avail-
able. Contact a National Sem ..
DM74LS670N ,3-STATE 4-by-4 Register FileGeneral Description
These register tiles are organized as 4 words of 4 bits each,
and separate ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsGeneral DescriptionThis device contains two independent negative-edge-trig-gered J-K flip-flops wit ..
DM74LS73AN ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsDM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Out ..
DS2415 ,1-Wire Time ChipPIN DESCRIPTION Built-in multidrop controller ensurescompatibility with other MicroLAN products Pi ..
DS2415P ,1-Wire Time Chipfeaturescan be used to add functions such as calendar, time and date stamp and logbook to any type ..
DS2415P/T&R ,1-Wire Time ChipPIN DESCRIPTION Built-in multidrop controller ensurescompatibility with other MicroLAN products Pi ..
DS2415P-W ,1-Wire Time Chipfeaturescan be used to add functions such as calendar, time and date stamp, and logbook to any type ..
DS2423P ,4kbit 1-Wire RAM with CounterPIN DESCRIPTIONcompatibility with other MicroLAN productsPin 1 Ground Directly connects to a singl ..
DS2430 ,256-Bit 1-Wire EEPROMblock diagram in Figure 1 shows the relationships between the major control and memory sections oft ..
DM74LS670MX
3-STATE 4-by-4 Register File
DM74LS670 3-STATE 4-by-4 Register File August 1986 Revised March 2000 DM74LS670 3-STATE 4-by-4 Register File nates recovery times, permits simultaneous reading and General Description writing, and is limited in speed only by the write time (27 ns These register files are organized as 4 words of 4 bits typical) and the read time (24 ns typical). The register file each, and separate on-chip decoding is provided for has a non-volatile readout in that data is not lost when addressing the four word locations to either write-in or addressed. retrieve data. This permits writing into one location, and All inputs (except read enable and write enable) are buff- reading from another word location, simultaneously. ered to lower the drive requirements to one normal Series Four data inputs are available to supply the word to be DM74LS load, and input clamping diodes minimize switch- stored. Location of the word is determined by the write ing transients to simplify system design. High speed, dou- select inputs A and B, in conjunction with a write-enable ble ended AND-OR-INVERT gates are employed for the signal. Data applied at the inputs should be in its true form. read-address function and have high sink current, 3-STATE That is, if a high level signal is desired from the output, a outputs. Up to 128 of these outputs may be wire-AND con- high level is applied at the data input for that particular bit nected for increasing the capacity up to 512 words. Any location. The latch inputs are arranged so that new data number of these registers may be paralleled to provide n- will be accepted only if both internal address gate inputs bit word length. are HIGH. When this condition exists, data at the D input is transferred to the latch output. When the write-enable Features input, G , is HIGH, the data inputs are inhibited and their W � For use as: levels can cause no change in the information stored in the internal latches. When the read-enable input, G , is HIGH, Scratch pad memory R the data outputs are inhibited and go into the high imped- Buffer storage between processors ance state. Bit storage in fast multiplication designs The individual address lines permit direct acquisition of � Separate read/write addressing permits simultaneous data stored in any four of the latches. Four individual reading and writing decoding gates are used to complete the address for read- � Organized as 4 words of 4 bits ing a word. When the read address is made in conjunction � Expandable to 512 words of n-bits with the read-enable signal, the word appears at the four outputs. � 3-STATE versions of DM74LS170 This arrangement—data entry addressing separate from � Fast access times 20 ns typ data read addressing and individual sense line — elimi- Ordering Code: Order Number Package Number Package Description DM74LS670M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS670N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006436
