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DM74LS395N
4-Bit Shift Register with TRI-STATE Outputs
TL/F/9833
DM74LS395
4-Bit
Shift
Register
with
TRI-STATE
Outputs
February 1992
DM74LS395
4-Bit Shift Register with TRI-STATEÉ Outputs
General Description
The LS395isa 4-bit shift register with TRI-STATE outputs
andcan operatein eithera synchronous parallel loadora
serialshift-right mode, asdeterminedbythe Select input.An
asynchronous active LOW Master Reset (MR) input over-
ridesthe synchronous operations and clearsthe register. active LOW Output Enable (OE) input controlsthe TRI-
STATE output buffers,but doesnot interfere withthe other
operations.The fourth stage alsohasa conventional output
for linking purposesin multi-stage serial operations.
Features Shift rightor parallel 4-bit register TRI-STATE outputs Input clamp diodes limit high speed termination effects Fully CMOSand TTL compatible
Connection Diagram
Dual-In-Line Package
TL/F/9833–1
Order Number DM74LS395WM orDM74LS395N
SeeNS PackageNumberM16Bor N16E
Logic Symbol
TL/F/9833–2
VCCePin16
GNDePin8
Mode Select Table
Operating Mode Inputs@tn Outputs@ tna1 CP SDSPn O0 O1 O2 O3
Asynchronous Reset L XXXXL L L L
Shift, SET First Stage H K LHX H O0n O1n 02n
Shift, RESETFirst StageH K LLXL O0n O1n 02n
Parallel Load H K HXPnP0 P1 P2 P3
tn,tna1e TimebeforeandafterCP HIGH-to-LOW transitione HIGH Voltage Levele LOWVoltage Levele Immaterial
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
