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DM74LS393MXFAIRN/a321avai Dual 4-Bit Binary Counter


DM74LS393MX , Dual 4-Bit Binary CounterDM74LS393 Dual 4-Bit Binary CounterAugust 1986Revised March 2000DM74LS393Dual 4-Bit Binary Counter
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DM74LS393MX
Dual 4-Bit Binary Counter
DM74LS393 Dual 4-Bit Binary Counter August 1986 Revised March 2000 DM74LS393 Dual 4-Bit Binary Counter General Description Features Each of these monolithic circuits contains eight master- � Dual version of the popular DM74LS93 slave flip-flops and additional gating to implement two indi- � DM74LS393 dual 4-bit binary counter with individual vidual four-bit counters in a single package. The clocks DM74LS393 comprises two independent four-bit binary � Direct clear for each 4-bit counter counters each having a clear and a clock input. N-bit binary � Dual 4-bit versions can significantly improve system counters can be implemented with each package providing densities by reducing counter package count by 50% the capability of divide-by-256. The DM74LS393 has paral- lel outputs from each counter stage so that any submultiple � Typical maximum count frequency 35 MHz of the input count frequency is available for system-timing � Buffered outputs reduce possibility of collector commu- signals. tation Ordering Code: Order Number Package Number Package Description DM74LS393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS373N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Counter Sequence (Each Counter) Outputs Count Q Q Q Q D C B A 0 LLLL 1 LLL H 2L L H L 3L L H H 4L H L L 5L H L H 6L H H L 7 L HHH 8 H LLL 9H L L H 10 HL HL 11 H L H H 12 H H L L 13 H H L H 14 HHH L 15 HHHH H = HIGH Logic Level L = LOW Logic Level © 2000 DS006434
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