DM74LS377N ,Octal D Flip-Flop with Common Enable and ClockFunctional DescriptionThe DM74LS377 consists of eight edge-triggered D flip-flops with individual D ..
DM74LS377WMX , Octal D Flip-Flop with Common Enable and ClockFunctional DescriptionThe DM74LS377 consists of eight edge-triggered D flip-flops with individual D ..
DM74LS37N , QUAD 2-INPUT NAND BUFFERS
DM74LS380N ,7 V, multifunction octal registerElectrical Characteristics Over Operating Conditions
Symbol Parameter Test Condilions Mln Typt I M ..
DM74LS38M ,Quad 2-Input NAND Buffer with Open-Collector OutputsDM74LS38 Quad 2-Input NAND Buffer with Open-Collector OutputsAugust 1986Revised March 2000DM74LS38Q ..
DM74LS38M ,Quad 2-Input NAND Buffer with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates, each of ..
DS2401X1#U ,Silicon Serial NumberFEATURES PIN ASSIGNMENT Upgrade and drop-in replacement for DS2400TO-92TSOC PACKAGE— Extended 2.8 ..
DS2401Z ,Silicon Serial NumberPIN DESCRIPTIONmicroprocessor and communicates at up toTO-92/SOT-223 TSOC16.3 kbits/sPin 1 Ground G ..
DS2401Z+ ,Silicon Serial NumberDS2401Silicon Serial Number
DS2404 ,EconoRAM Time Chippin description and “Power Control” section.) BATO10 V Battery operate input pin for 2.8V to 5.5V o ..
DS2404-001 ,EconoRAM Time Chippin description and “Power Control” section.)BATO10 V Battery operate input pin for 2.8 to 5.5 volt ..
DS2404B ,EconoRAM Time ChipFEATURES PIN ASSIGNMENT§ 4096 bits of nonvolatile dual-port memoryVCC 1 16 VCCincluding real time c ..
DM74LS377N
Octal D-Type Flip-Flop with Common Enable and Clock
DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock October 1988 Revised March 2000 DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock General Description Features The DM74LS377 is an 8-bit register built using advanced � 8-bit high speed parallel registers low power Schottky technology. This register consists of � Positive edge-triggered D-type flip-flops eight D-type flip-flops with a buffered common clock and a � Fully buffered common clock and enable inputs buffered common input enable. The device is packaged in the space-saving (0.3 inch row spacing) 20-pin package. Ordering Code: Order Number Package Number Package Description DM74LS377WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS377N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram V = Pin 20 CC GND = Pin 10 Pin Descriptions Truth Table Pin Names Description Inputs Output E Enable Input (Active LOW) D Q E CP n n D0–D7 Data Inputs H X X No Change CP Clock Pulse Input (Active Rising Edge) LHH Q0–Q7 Flip-Flop Outputs LLL H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © 2000 DS009831
