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DM74LS323NNSN/a41avai8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins


DM74LS323N ,8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pinsapplicationsparallel load. All modes are activated on the LOW-to-HIGHtransition of the Clock.Connec ..
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DM74LS32N ,Quad 2-Input OR GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic OR f ..
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DS229 ,Triple RS-232 Transmitter/ReceiverFEATURES PIN ASSIGNMENT Compatible with DS1229VC1+ 1 20 CCV+ 19GND 5V operation 2C1-3 18 T1OUT 2 ..
DS229EN+ ,Triple RS-232 Transmitter/ReceiverFEATURES PIN ASSIGNMENT Compatible with DS1229VC1+ 1 20 CCV+ 19GND 5V operation 2C1-3 18 T1OUT 2 ..
DS229N ,Triple RS-232 Transmitter/Receiverapplications V- T1INT2T2OUT 7 14 IN Operate from single +5V powerR2 8 13IN R2OUT Meets all EIA-23 ..
DS229S ,Triple RS-232 Transmitter/ReceiverPIN DESCRIPTIONORDERING INFORMATIONV - +5-Volt SupplyCCDS229 20-pin DIPGND - GroundDS229N 20-pin DI ..
DS229S+ ,Triple RS-232 Transmitter/ReceiverPIN DESCRIPTIONORDERING INFORMATIONV - +5-Volt SupplyCCDS229 20-pin DIPGND - GroundDS229N 20-pin DI ..
DS229SN ,Triple RS-232 Transmitter/ReceiverFEATURES PIN ASSIGNMENT Compatible with DS1229VC1+ 1 20 CCV+ 19GND 5V operation 2C1-3 18 T1OUT 2 ..


DM74LS323N
8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
TL/F/9829
DM54LS323/DM74LS323
8-Bit
Universal
Shift/Storage
Register
with
Synchronous
Reset
and
Common
I/O
Pins
April 1992
DM54LS323/DM74LS323
8-Bit Universal Shift/Storage Register
with Synchronous Reset and Common I/O Pins
General Description
The ’LS323isan 8-bit universal shift/storage register with
TRI-STATEÉ outputs.Its functionis similartothe ’LS299
withthe exceptionof Synchronous Reset. Parallel loadin-
puts and flip-flop outputsare multiplexedto minimizepin
count. Separate inputs and outputsare providedforflip-
flopsQ0 andQ7to allow easy cascading. Four operation
modesare possible: hold (store), shiftleft, shift right,and
parallel load.All modesare activatedonthe LOW-to-HIGH
transitionofthe Clock.
Features CommonI/Ofor reducedpin count Four operation modes: shiftleft, shift right, parallel load
and store Separate continuous inputs and outputs fromQ0 and allow easy cascading Fully synchronous reset TRI-STATE outputsforbus oriented applications
Connection Diagram
Dual-In-Line Package
TL/F/9829–1
Order Number DM54LS323J,DM54LS323W, DM74LS323WMor DM74LS323N
SeeNS Package Number J20A,M20B,N20Aor W20A
PinNames Description ClockPulseInput (Active Rising Edge)
DS0 SerialData InputforRightShift
DS7 SerialData InputforLeft Shift
S0,S1 ModeSelect Inputs Synchronous Reset Input (Active LOW)
OE1, OE2 TRI-STATEOutput Enable Inputs(Active LOW)
I/O0–I/O7 Parallel DataInputsor TRI-STATE
Parallel Outputs
Q0,Q7 SerialOutputs
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
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