DM74LS257BN ,TRI-STATE Quad 2-Data Selectors/MultiplexersGeneral Descriptionisters for data retention throughout the system.These Schottky-clamped high-perf ..
DM74LS258BN ,TRI-STATE Quad 2-Data Selectors/MultiplexersFeaturesYTRI-STATE versions LS157 and LS158 with same pin-These Schottky-clamped high-performance m ..
DM74LS259M ,8-Bit Addressable LatchesDM74LS259 8-Bit Addressable LatchesAugust 1986Revised March 2000DM74LS2598-Bit Addressable Latches
DM74LS259N ,8-Bit Addressable LatchesFeaturesThese 8-bit addressable latches are designed for general 8-Bit parallel-out storage regist ..
DM74LS259WM ,8-Bit Addressable Latches
DM74LS266MX , Quad 2-Input Exclusive NOR Gate with Open Collector OutputsGeneral DescriptionThis device contains four independent gates each of whichperforms the logic excl ..
DS21S07AE ,SCSI TerminatorGENERAL DESCRIPTION PIN CONFIGURATIONS Fast SCSI and Ultra SCSI require the use of active terminati ..
DS21S07AS ,SCSI TerminatorFEATURES Fully Compliant with SCSI-1, Fast SCSI, and Ultra SCSI Backward Compatible to the DS2107 ..
DS21S07AS/TR , SCSI Terminator
DS21T05 ,SCSI TerminatorFUNCTIONAL DESCRIPTIONThe DS21T05 consists of a bandgap reference, buffer amplifier, and nine termi ..
DS21T05Z+ ,SCSI TerminatorFUNCTIONAL DESCRIPTIONThe DS21T05 consists of a bandgap reference, buffer amplifier, and nine termi ..
DS21T06 , SCSI Terminator
DM74LS257BN
3-STATE Quad 2-Data Selectors/Multiplexers
DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers June 1989 Revised November 1999 DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers for data buses. It also permits the use of standard TTL reg- General Description isters for data retention throughout the system. These Schottky-clamped high-performance multiplexers feature 3-STATE outputs that can interface directly with Features data lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the3-STATE versions LS157 and LS158 with same pinouts low impedance of the single enabled output will drive theSchottky-clamped for significant improvement in A-C bus line to a HIGH or LOW logic level. To minimize the pos- performance sibility that two outputs will attempt to take a common bus Provides bus interface from multiple sources in to opposite logic levels, the output enable circuitry is high-performance systems designed such that the output disable times are shorter Average propagation delay from data input 12 ns than the output enable times. Typical power dissipation: 50 mW This 3-STATE output feature means that n-bit (paralleled) data selectors with up to 258 sources can be implemented Ordering Code: Order Number Package Number Package Description DM74LS257BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS257BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Function Table Inputs Output Y Output Select A B LS257 Control HX X X Z LL L X L LL H X H LH X L L LH X H H H = HIGH Level X = Don’t Care L = LOW Level Z = High Impedance (off) © 1999 DS006417
