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DS21S07AE ,SCSI TerminatorGENERAL DESCRIPTION PIN CONFIGURATIONS Fast SCSI and Ultra SCSI require the use of active terminati ..
DS21S07AS ,SCSI TerminatorFEATURES Fully Compliant with SCSI-1, Fast SCSI, and Ultra SCSI Backward Compatible to the DS2107 ..
DS21S07AS/TR , SCSI Terminator
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DM74LS256N
Dual 4-Bit Addressable Latch
TL/F/9823
54LS256/DM74LS256
Dual
4-Bit
Addressable
Latch
June 1989
54LS256/DM74LS256
Dual 4-Bit Addressable Latch
General Description
The ’LS256isa dual 4-bit addressable latch with common
control inputs; these includetwo Address inputs (A0, A1), active LOW enable input(E) andan active LOW Clear
input (CL). Each latchhasa Data input(D)andfour outputs
(Q0–Q3).
Whenthe Enable(E)is HIGH andthe Clear input (CL)is
LOW,all outputs (Q0–Q3)are LOW. Dual 4-channel demul-
tiplexing occurs whentheCLandEare both LOW. Whenis HIGH andEis LOW,the selected output (Q0–Q3),
determinedbythe Address inputs, followsD. WhentheE
goes HIGH,the contentsofthe latchare stored. Whenop-
eratinginthe addressable latch mode(Ee LOW,CLe
HIGH), changing more thanonebitofthe Address(A0,A1)
could imposea transient wrong address. Therefore, this
shouldbe doneonly whileinthe memory mode(EeCLe
HIGH).
Features Serial-to-parallel capability Output from each storagebit available Random (addressable) data entry Easily expandable Activelow common clear
Connection Diagram
Dual-In-Line Package
TL/F/9823–1
Order Number 54LS256DMQB,
54LS256FMQB orDM74LS256N
See NSPackageNumber J16A,
N16Eor W16A
Logic Symbol
TL/F/9823–2
VCCePin16
GND ePin8
Pin Names Description
A0,A1 Common Address Inputs
Da,Db Data Inputs Common Enable Input(Active LOW) ConditionalClear Input (Active LOW)
Q0a–Q3a SideA Latch Outputs
Q0b–Q3b SideB Latch Outputs
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
