DM74LS244WMX , Octal 3-STATE Buffer/Line Driver/Line ReceiverFeaturesThese buffers/line drivers are designed to improve both the ■ 3-STATE outputs drive bus lin ..
DM74LS245N ,3-STATE Octal Bus TransceiverFeaturesThese octal bus transceivers are designed for asynchro- ■ Bi-Directional bus transceiver in ..
DM74LS245SJX , Octal 3-STATE Bus TransceiverDM74LS245 3-STATE Octal Bus TransceiverAugust 1986Revised March 2000DM74LS2453-STATE Octal Bus Tran ..
DM74LS245WM ,3-STATE Octal Bus TransceiverFeatures YAlternate Military/Aerospace device (54LS245) is avail-YBi-Directional bus transceiver in ..
DM74LS245WMX , Octal 3-STATE Bus TransceiverFeaturesThese octal bus transceivers are designed for asynchro- ■ Bi-Directional bus transceiver in ..
DM74LS247N ,V(cc): 4.75 to 5.25V; BCD to 7-segment decoder/driver with open collector outputsGeneral Description
The 'LS247 has active LOW open-collector outputs guaran-
teed to sink 24 mA ..
DS21Q43AT+ ,Quad E1 Framerapplications that require more than one E1 framer on acard. The Quad version is only slightly bigge ..
DS21Q44T ,Enhanced QUAD E1 FRAMERapplicationsORDERING INFORMATION Integral HDLC controller with 64-byte buffers 0 0DS21Q44T (0 C to ..
DS21Q44T ,Enhanced QUAD E1 FRAMERFEATURES FUNCTIONAL DIAGRAM Four E1 (CEPT or PCM-30) /ISDN-PRIframing transceiversRece ive Elastic ..
DS21Q48 ,5V E1/T1/J1 Line InterfacePIN DESCRIPTION 10 3 HARDWARE MODE ....... 23 3.1 REGISTER MAP ........23 3.2 PARALLEL PORT OPERATI ..
DS21Q48A3N ,5V E1/T1/J1 Line InterfaceFEATURES Complete E1, T1, or J1 Line Interface Unit TOP VIEW 44(LIU) Supports Both Long- and ..
DS21Q50 ,Quad E1 TransceiverFEATURES The DS21Q50 E1 quad transceiver contains all the Four Complete E1 (CEPT) PCM-30/ISDN-PRI ..
DM74LS244WMX
Octal 3-STATE Buffer/Line Driver/Line Receiver
DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver August 1986 Revised March 2000 DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description Features These buffers/line drivers are designed to improve both the � 3-STATE outputs drive bus lines directly performance and PC board density of 3-STATE buffers/ � PNP inputs reduce DC loading on bus lines drivers employed as memory-address drivers, clock driv- � Hysteresis at data inputs improves noise margins ers, and bus-oriented transmitters/receivers. Featuring 400 � Typical I (sink current) 24 mA OL mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout out- � Typical I (source current) −15 mA OH puts and can be used to drive terminated lines down to � Typical propagation delay times 133Ω. Inverting 10.5 ns Noninverting 12 ns � Typical enable/disable time 18 ns � Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW Ordering Code: Order Number Package Number Package Description DM74LS244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Output G AY LLL LH H HX Z L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level Z = High Impedance © 2000 DS008442
