DM74LS240WMX , Octal 3-STATE Buffer/Line Driver/Line Receiver (Inverting)FeaturesThese buffers/line drivers are designed to improve both the ■ 3-STATE outputs drive bus lin ..
DM74LS241N ,Octal TRI-STATE Buffers/Line Drivers/Line ReceiversFeaturesThese buffers/line drivers are designed to improve both the ■ 3-STATE outputs drive bus lin ..
DM74LS241WM ,Octal 3-STATE Buffer/Line Driver/Line Receiver
DM74LS243N ,Quadruple Bus Transceiver
DM74LS243N ,Quadruple Bus TransceiverFeaturesThis four data line transceiver is designed for asynchro- ■ Two-way asynchronous communicat ..
DM74LS243WM ,7 V, quadruple bus transceiver
DS21Q348N ,3.3V E1/T1/J1 line interfacePIN DESCRIPTION Complete E1, T1, or J1 line interface unit44(LIU) Supports both long-haul and sho ..
DS21Q352 ,Quad T1/E1 Transceiver (3.3V,5.0V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q352B+ ,Quad T1/E1 Transceiver (3.3V, 5.0V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q354 ,Quad E1 Transceiver (3.3V)DALLAS SEMICONDUCTOR PreliminaryQuad T1/E1 Transceiver (5V) DS21Q552/DS21Q554Quad T1/E1 Transceiver ..
DS21Q354B ,Quad T1/E1 Transceiver (3.3V, 5.0V)FEATURESP• Four (4) Completely Independent T1 or E1 Transceivers In One Small 27mm x 27mm Package • ..
DS21Q41B ,Quad T1 Framerapplications that require more than one T1 framer on a card. TheQuad version is only slightly bigge ..
DM74LS240WMX
Octal 3-STATE Buffer/Line Driver/Line Receiver (Inverting)
DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver August 1986 Revised March 2000 DM74LS240 • DM74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description Features These buffers/line drivers are designed to improve both the � 3-STATE outputs drive bus lines directly performance and PC board density of 3-STATE buffers/ � PNP inputs reduce DC loading on bus lines drivers employed as memory-address drivers, clock driv- � Hysteresis at data inputs improves noise margins ers, and bus-oriented transmitters/receivers. Featuring � Typical I (sink current) OL 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high 24 mA fanout outputs and can be used to drive terminated lines � Typical I (source current) OH down to 133Ω. −15 mA � Typical propagation delay times Inverting 10.5 ns Noninverting 12 ns � Typical enable/disable time 18 ns � Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW Ordering Code: Order Number Package Number Package Description DM74LS240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS241WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS241N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS240 DM74LS241 © 2000 DS006411
