DM74LS194AN ,4-Bit Bidirectional Universal Shift Registerfeatures a system designer may want in a■ Four operating modes:shift register; they feature paralle ..
DM74LS195AN ,7 V, 4-bit parallel access shift registerElectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recomm ..
DM74LS195AN ,7 V, 4-bit parallel access shift registerfeatures parallel inputs, parallel outputs, I Synchronous parallel Ioad
J-R serial inputs, shift ..
DM74LS20M ,Dual 4-Input NAND GateDM74LS20 Dual 4-Input NAND GateJune 1986Revised March 2000DM74LS20Dual 4-Input NAND Gate
DM74LS20N ,Dual 4-Input NAND GatesGeneral DescriptionThis device contains two independent gates each of whichperforms the logic NAND ..
DM74LS21 ,Dual 4-Input AND GateFeaturesYAlternate Military/Aerospace device (54LS21) is avail-This device contains two independent ..
DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2187+ ,Receive Line Interfaceapplications utilize a 18.528 MHz clock divided by either11, 12, or 13 to match the phase of the in ..
DS2187S ,Receive Line Interfaceapplications. Special internal circuitry of the RTIP and RRINGinputs permits negative signal excurs ..
DS2187S ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2188 ,T1/CEPT Jitter AttenuatorFEATURES PIN ASSIGNMENT Attenuates clock and data jitter present in T1 DJA 1 16 VDDo ..
DS2188S ,T1/CEPT Jitter AttenuatorDS2188T1/CEPT Jitter Attenuatorwww.dalsemi.com
DM74LS194AN
4-Bit Bidirectional Universal Shift Register
DM74LS194A 4-Bit Bidirectional Universal Shift Register August 1986 Revised March 2000 DM74LS194A 4-Bit Bidirectional Universal Shift Register General Description Features This bidirectional shift register is designed to incorporate � Parallel inputs and outputs virtually all of the features a system designer may want in a � Four operating modes: shift register; they feature parallel inputs, parallel outputs, Synchronous parallel load right-shift and left-shift serial inputs, operating-mode-con- Right shift trol inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Left shift Do nothing Parallel (broadside) load Shift right (in the direction Q toward Q ) � Positive edge-triggered clocking A D � Direct overriding clear Shift left (in the direction Q toward Q ) D A Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after the positive transi- tion of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are LOW. Ordering Code: Order Number Package Number Package Description DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006407
