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I Fully independent clear input
I Synchronous operation
I Cascading circuitry pro ..
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Synchronous ope ..
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DS2186S ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
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DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
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DM74LS192N
54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks
TL/F/10178
54LS192/DM74LS192
Up/Down
Decade
Counter
with
Separate
Up/Down
Clocks
May 1992
54LS192/DM74LS192 Up/Down Decade Counter
with Separate Up/Down Clocks
General Description
The ’LS192isan up/down BCD decade (8421) counter.
Separate Count Upand Count Down Clocksare usedandin
either counting modethe circuits operate synchronously.
The outputs change state synchronous withthe LOW-to-
HIGH transitionsonthe clock inputs.
Separate Terminal CountUpand Terminal Count Downout-
putsare provided whichare usedasthe clocksfora subse-
quent stage without extra logic, thus simplifying multistage
counter designs.Individual preset inputsallowthe circuitsto usedas programmable counters. Boththe Parallel Load
(PL) andthe Master Reset (MR) inputs asynchronously
overridethe clocks.
Connection Diagram
Dual-In-Line Package
TL/F/10178–1
Order Number 54LS192DMQB, 54LS192FMQB,
54LS192LMQB, DM74LS192Mor DM74LS192N
SeeNS Package Number E20A, J16A,
M16A, N16Eor W16A
Logic Symbol
TL/F/10178–2
VCCePin16
GNDePin8
PinNames Description
CPU Count UpClock Input
(Active Rising Edge)
CPD Count DownClock Input
(Active Rising Edge) AsynchronousMaster Reset Input
(Active HIGH) AsynchronousParallelLoad Input
(Active LOW)
P0–P3 Parallel Data Inputs
Q0–Q3 Flip-FlopOutputs
TCD Terminal CountDown (Borrow)
Output (ActiveLOW)
TCU Terminal CountUp (Carry)
Output (ActiveLOW)
Mode SelectTable PL CPU CPD Mode X X X Reset(Asyn.) L X X Preset (Asyn.) H H H No Change L H CountUp H L CountDowne HIGH Voltage LeveleLOW VoltageLevele Immaterial
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
