DM74LS191N ,Synchronous 4-Bit Up/Down Counters with Mode ControlGeneral Descriptioncading function: ripple clock and maximum/minimum count.The DM74LS191 circuit is ..
DM74LS192N ,54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks54LS192/DM74LS192Up/DownDecadeCounterwithSeparateUp/DownClocksMay199254LS192/DM74LS192Up/DownDecade ..
DM74LS192N ,54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks54LS192/DM74LS192Up/DownDecadeCounterwithSeparateUp/DownClocksMay199254LS192/DM74LS192Up/DownDecade ..
DM74LS193MX , Synchronous 4-Bit Up/Down Binary Counter with Dual ClockGeneral Descriptioninputs are buffered to lower the drive requirements of clockThe DM74LS193 circui ..
DM74LS193N ,Synchronous 4-Bit Binary Counter with Dual ClockFeatures
I Fully independent clear input
I Synchronous operation
I Cascading circuitry pro ..
DM74LS193N ,Synchronous 4-Bit Binary Counter with Dual ClockGeneral Description
This circuit is a synchronous up/down 4-bit binary counter.
Synchronous ope ..
DS2186+ ,Transmit Line InterfacePIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 TAIS I Transmit Alarm Indication Signal. When ..
DS2186S ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DS2186S ,Transmit Line InterfaceBLOCK DIAGRAM Figure 1VSSLNEGLPOSTTIPLCLKINPUT ZERO CODELINEWAVESHAPPINGDATA SUPPRESSIONDRIVERSTNEG ..
DS2186S+ ,Transmit Line Interfaceapplications are supported. Appropriate CCITT recom-communications networks. The device is compatib ..
DS2187 ,Receive Line Interfaceapplications such as AVSS 10 11 DVSSterminal equipment to DSX-1 20-Pin S ..
DS2187+ ,Receive Line Interfaceapplications utilize a 18.528 MHz clock divided by either11, 12, or 13 to match the phase of the in ..
DM74LS191N
Synchronous 4-Bit Up/Down Counter with Mode Control
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control Two outputs have been made available to perform the cas- General Description cading function: ripple clock and maximum/minimum count. The DM74LS191 circuit is a synchronous, reversible, up/ The latter output produces a high-level output pulse with a down counter. Synchronous operation is provided by hav- duration approximately equal to one complete cycle of the ing all flip-flops clocked simultaneously, so that the outputs clock when the counter overflows or underflows. The ripple change simultaneously when so instructed by the steering clock output produces a low-level output pulse equal in logic. This mode of operation eliminates the output count- width to the low-level portion of the clock input when an ing spikes normally associated with asynchronous (ripple overflow or underflow condition exists. The counters can be clock) counters. easily cascaded by feeding the ripple clock output to the The outputs of the four master-slave flip-flops are triggered enable input of the succeeding counter if parallel clocking on a LOW-to-HIGH level transition of the clock input, if the is used, or to the clock input if parallel enabling is used. enable input is LOW. A HIGH at the enable input inhibits The maximum/minimum count output can be used to counting. Level changes at either the enable input or the accomplish look-ahead for high-speed operation. down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level Features of the down/up input. When LOW, the counter counts up � Counts binary and when HIGH, it counts down. � Single down/up count control line The counter is fully programmable; that is, the outputs may � Count enable control input be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output � Ripple clock output for cascading will change independent of the level of the clock input. This � Asynchronously presettable with load control feature allows the counters to be used as modulo-N divid- � Parallel outputs ers by simply modifying the count length with the preset � Cascadable for n-bit applications inputs. � Average propagation delay 20 ns The clock, down/up, and load inputs are buffered to lower the drive requirement; which significantly reduces the num- � Typical clock frequency 25 MHz ber of clock drivers, etc., required for long parallel words. � Typical power dissipation 100 mW Ordering Code: Order Number Package Number Package Description DM74LS191M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 DS006405.prf
