DM74LS175MX , Quad D Flip-Flop with Clear and Complementary OutputsApplications include:ular voltage level and is not directly related to the transitionBuffer/storage ..
DM74LS175N ,Hex/Quad D Flip-Flops with ClearFeaturesYLS174 contains six flip-flops with single-rail outputsThese positive-edge-triggered flip-f ..
DM74LS175SJ ,Hex/Quad D-Type Flip-Flops with ClearDM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with ClearAugust 1992Revised April 2000DM74LS174 • ..
DM74LS181N ,4-Bit Arithmetic Logic Unit
DM74LS181N ,4-Bit Arithmetic Logic Unit
DM74LS190N ,Synchronous 4-Bit Up/Down Counters with Mode ControlDM54LS190/DM74LS190,DM54LS191/DM74LS191Synchronous4-BitUp/DownCounterswithModeControlMay1989DM54LS1 ..
DS2181A ,CEPT Primary Rate TransceiverFEATURES PIN ASSIGNMENT Single chip primary rate transceiver meets TMSYNC 1 40 VDDCCITT stand ..
DS2181A ,CEPT Primary Rate Transceiverfeatures such as error logging, per-channel code manipulation, and alteration ofthe receive synchro ..
DS2181A+ ,CEPT Primary Rate TransceiverBLOCK DIAGRAM Figure 1 2 of 32DS2181ATRANSMIT
DS2181AQ ,CEPT Primary Rate Transceiverfeatures such as error logging, per-channel code manipulation, and alteration ofthe receive synchro ..
DS2182 ,T1 Line MonitorFEATURESchanges from the original DS2182:§ Performs framing and monitoring functions§ Ability to co ..
DS2186 ,Transmit Line Interfaceapplications.DD4 LEN0 I Length Select 0, 1 and 2. State determines output T1 waveform5 LEN1 shape ..
DM74LS175MX
Quad D Flip-Flop with Clear and Complementary Outputs
DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear August 1992 Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry � DM74LS174 contains six flip-flops with single-rail to implement D-type flip-flop logic. All have a direct clear outputs input, and the quad (175) versions feature complementary � DM74LS175 contains four flip-flops with double-rail outputs from each flip-flop. outputs Information at the D inputs meeting the setup time require- � Buffered clock and direct clear inputs ments is transferred to the Q outputs on the positive-going � Individual data input to each flip-flop edge of the clock pulse. Clock triggering occurs at a partic- � Applications include: ular voltage level and is not directly related to the transition Buffer/storage registers time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no Shift registers effect at the output. Pattern generators � Typical clock frequency 40 MHz � Typical power dissipation per flip-flop 14 mW Ordering Code: Order Number Package Number Package Description DM74LS174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74LS174 DM74LS175 © 2000 DS006404
