DM74LS174N ,Hex/Quad D-Type Flip-Flops with ClearFeaturesYLS174 contains six flip-flops with single-rail outputsThese positive-edge-triggered flip-f ..
DM74LS175M ,Hex/Quad D Flip-Flops with ClearDM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with ClearAugust 1992Revised April 2000DM74LS174 • ..
DM74LS175MX , Quad D Flip-Flop with Clear and Complementary OutputsApplications include:ular voltage level and is not directly related to the transitionBuffer/storage ..
DM74LS175N ,Hex/Quad D Flip-Flops with ClearFeaturesYLS174 contains six flip-flops with single-rail outputsThese positive-edge-triggered flip-f ..
DM74LS175SJ ,Hex/Quad D-Type Flip-Flops with ClearDM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with ClearAugust 1992Revised April 2000DM74LS174 • ..
DM74LS181N ,4-Bit Arithmetic Logic Unit
DS2180A ,T1 TransceiverFEATURES PIN ASSIGNMENT Single chip DS1 rate transceiver TMSYNC 1 40 VDD Supports common fra ..
DS2180A+ ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AN ,T1 TransceiverPIN DESCRIPTION (40-PIN DIP ONLY) Table 1PIN SYMBOL TYPE DESCRIPTION1 TMSYNC I Transmit Multiframe ..
DS2180AQ ,T1 TransceiverBLOCK DIAGRAM Figure 1 2 of 35DS2180ATRANSMIT
DS2180AQ+ ,T1 TransceiverFEATURES PIN ASSIGNMENT Single chip DS1 rate transceiver TMSYNC 1 40 VDD Supports common fra ..
DS2180AQN ,T1 Transceiverapplications (12frames/superframe). The 193E framing mode supports the extended superframe format ..
DM74LS174N-DM74LS175N
Hex/Quad D Flip-Flops with Clear
TL/F/6404
54LS174/DM54LS174/DM74LS174,
54LS175/DM54LS175/DM74LS175
Hex/Quad
Flip-Flops
with
Clear
June 1989
54LS174/DM54LS174/DM74LS174,
54LS175/DM54LS175/DM74LS175
Hex/QuadD Flip-Flops with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry implement D-type flip-flop logic.All havea direct clear
input,andthe quad (175) versions feature complementary
outputs from each flip-flop.
InformationattheD inputs meetingthe setup time require-
mentsis transferredtotheQ outputsonthe positive-going
edge ofthe clockpulse. Clock triggering occursata particu-
lar voltage levelandisnot directly relatedtothe transition
timeofthe positive-going pulse. Whenthe clock inputisat
eitherthe highorlow level,theD input signalhasno effectthe output.
Features LS174 containssix flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clockand direct clear inputs Individual data inputto each flip-flop Applications include:
Buffer/storage registers
Shift registers
Pattern generators Typical clock frequency40 MHz Typical power dissipationper flip-flop14 mW Alternate Military/Aerospace device (54LS174,
54LS175)is available. Contacta National Semiconduc-
tor Sales Office/Distributorfor specifications.
Connection Diagrams
Dual-In-Line Package
TL/F/6404–1
Order Number 54LS174DMQB, 54LS174FMQB,
54LS174LMQB,DM54LS174J,
DM54LS174W, DM74LS174Mor DM74LS174N
SeeNS Package Number E20A, J16A,
M16A, N16Eor W16A
Dual-In-Line Package
TL/F/6404–2
Order Number 54LS175DMQB, 54LS175FMQB,
54LS175LMQB, DM54LS175J
DM54LS175W, DM74LS175MorDM74LS175N
SeeNS Package Number E20A, J16A,
M16A,N16EorW16A
Function Table (EachFlip-Flop)
Inputs Outputs
Clear Clock D Q Q² X L H u HH L u LL H X Q0 Q0eHigh Level (steadystate)eLow Level (steadystate)e Don’tCaree TransitionfromlowtohighleveleThe levelofQbeforetheindicated steady-stateinputconditionswere
established.e LS175only
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
