DM74LS173AN ,7 V, TRI-STATE 4-bit D-type registerLS173
National
Semiconductor
54LS173/DM74LS173A
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DS2176 ,T1 Receive BufferPIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 I Signaling Inhibit. When low, ABCD signaling u ..
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DM74LS173AN
7 V, TRI-STATE 4-bit D-type register
National
Semiconductor
54LS173/DM74LS173A
TRl-STATE® 4-Bit D-Type Register
General Description
This four-bit register contains D-type flip-ttops with totem-
pole TRMOATE8 outputs, capable of driving highly capaci-
tive or low-impedance loads. The high-impedance state and
increased high-logic-Ievel drive provide these flitrflops with
the capability of driving the bus tines in a bus-organized sys»
tem without need for interface or pull-up components.
Gated enable inputs are provided for controlling the entry of
data into the flip-flops. When both data-enable inputs are
low, data at the D inputs are loaded into their respective flip-
flops on the next positive transition of the buffered clock
input. Gate output control inputs are also provided. When
both are low, the normal logic states of the four outputs are
available for driving the loads or bus lines. The outputs are
disabled independently from the level of the clock by a high
logic level at either output control input. The outputs then
present a high impedance and neither load nor drive the bus
line. Detailed operation is given in the truth table.
To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the output con-
trol circuitry is designed so that the average output disable
times are shorter than the average output enable times.
Features
tt TRl-STATE outputs interface directly with system bus
I: Gated output control lines for enabling or disabling the
outputs
a Fully independent clock eliminates restrictions for oper-
ating in one of two modes:
Parallel load
Do nothing (hold)
n For application as bus buffer registers
Connection Diagram
Dual-In-Llne Package
DATA ENABLE
DATA IWS IWS
Voc CLEAR D1 D2 " D4 G2 G1
" " " " " 11 l " l 9
CLEAR ttt 20 3D 4D DATA
ENABLE
|1|zaqse7a
u u 01 02 ea momentum
--' ---.--
oumn comma ouwu‘rs
TL/F/6403-1
Order Number 54LS17SDMGB, 54LS173FMOB,
54L$173LMOB. DM74LS173AM or DM74LS173AN
See NS Package Number EMA, J16A,
M16A, N16E or W16A
Function Table
Inputs
Data Output
Clear Clock Enable Data 0
G1 G2 D
H X X X X L
L L x x x 00
L t H X X th
L t X H X th
L t L L L L
L t L L H H
When either M or N (or both) is (are) high the output is
disabled to the high-impedance state; however.
sequential operation of the flip-flops is not affected.
H -- High Level (Steady State)
L = Low Levet (Steady State)
t --= Low-to-High LevelTransition
X = Don't Care (Any Input Including Transitions)
th = The Level of Q Before the Indicated Steady State Input Conditions
Were Established.
Absolute Maximum Ratings (Note)
if Mllltary/Atrrottpaee ttpetrified devices are required,
please contact the National Semiconductor Sales
Omtte/Diatrlttutttm for availability and apeclflcatlons.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range
54LS --55''Cto + 125'C
DM74LS
Storage Temperature Range
ty'C to + 70''C
- 65°C to + 150°C
Recommended Operating Conditions
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values thtfthed in the "EletttritNtl Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Opera ting Conditions" table will tittfintt
the conditions for actual device operation.
Symbol Parameter 54LS173 DM74LS173A Unlts
Mln Nom Max Min Nom Max
Vcc Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
" Low Level Input Voltage 0.7 0.8 V
'OH High Level Output Current -1 -2.6 mA
lot. Low Level Output Current 12 24 mA
fax Clock Frequency (Note 1) 30 0 30 MHz
Clock Frequency (Note 2) 0 20 MHz
tw Pulse Width Clock 20 17 ns
(Note 3) Clear 17 17
tsu Setup Time Enable 17 23 n s
(Note 3) Data 15 15
tH Hold Time Enable 0 0 ns
(Note 3) Data 5 0
ha Clear Release Time 10 10 ns
TA Free Air Operating Temperature - 55 125 0 70 (
Note 1: CL = 45 pF, RL - 667tt,TA = 25% and Vcc " 5V.
Note 2: CL = 150 pF, RL = 6670, TA = 25'C and VCC = 5V.
Note 3: TA = 25''C and Vcc = 5v.
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Mln ("13:55) Max Units
VI lnputClamp Voltage Vcc = Min, II = --18 mA -1,5 V
VOH High Level Output VCC = Min, ky, = Max 2 4 V
Voltage VIL = Max, VIH = Min .
VOL Low Level Output VCC = Min, kx == Max 54LS 0.4
Voltage " = Max,ViH T.''-" Min DM74 0.35 0.5 V
IOL = 4 mA, Vcc = Min DM74 0.25 0.4
II InputCurrent @ Max VCC = Max, V. = 7V
Input Voltage OA mA
llH High Level InputCurrent Vcc = Max, V. = 2.7V 20 ”A
lit. Low Level lnputCurrent Vcc = Max, W = 0.4V -0.4 mA
'OZH Off-State Output Current with High VCC = Max, V0 = 2.7V 20 A
Level OutputVoltage Applied " = Min, " = Max P‘
lozc Off-State Output Current with Low Vcc = Max, vo = 0.4V -20 A
Level Output Voltage Applied ve, = Min, VIL --- Max "
los Short Circuit Vcc = Max 54LS --20 -100 m A
Output Current (Note 6) DM74 _ 20 -100
'06 Supply Current Vcc = Max (Note 7) 17 30 mA
SLLS'I
Switching Characteristics at VCC = 5V and TA = 25°C (See Section 1 for Test Waveforms and Output Load)
54Ls DM74LS
From (Input) = th. = 150 pF
Symbol Parameter To (Output) Cc so pF “L = 667 n Unlts
Min Max Mln Max
fMAx Maximum Clock 30 20 n 5
Frequency
tpLH Propagation Delay Time Clock to 28 34 ns
Low to High Level Output Output
tPHL Propagation Delay Time Clock to 28 40 n s
High to Low Level Output Output
tpHL Propagation Delay Time Clear to 30 40 ns
High to Low Level Output Output
tPZH Output Enable Time Output Control 23 34 ns
to High Level Output (M or N) to Any Q
thL Output Enable Time Output Control 28 45 ns
to Low Level Output (M or N) to Any Q
tive Output Disable Time from Output Control 17 25 ns
High Level Output (Note 8) (M or N) to Any Cl
tPLZ Output Disable Time from Output Control 23 25 ns
Low Level Output (Note 8) (M or N) to Any Q
Not. 4: All typical: are at Vcc - 5V, TA " 25'0.
Not. s.. Not more than one output should he shorted at a time. and the duration should not exceed one second.
Not. 6: Ice is measured with all outputs open: Clear grounded after a momentary 4.W; N, G1. G2 and all data inputs grounded: and the CLOCK and M Input at
Natl P. A = 5 pF.
Logic Diagram
OUTPUT "
CONTROL N
DATA G1
ENABLE G2
(2) , )
(15) t,t C
, CLOCK
(3) ttt
(4) 02
TUF/MS-Z
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This file is the datasheet for the following electronic components:
54LS173LMQB - product/54Is173|mqb?HQS=TI-nu|I-nu||-dscatalog-df-pf-null-wwe
DM74LS173AM - product/dm74ls173am?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
DM74LS173AN - product/dm74ls173an?HQS=T|-nu|I-nulI-dscatalog-df-pf-nuII-wwe
54LS173FMQB - product/54Is173fmqb?HQS=T|-nul|—null-dscatalog-df—pf—nuII-wwe
54LS173DMQB - product/54ls173dmqb?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
