DM74LS166N ,8-Bit Parallel-In/Serial-Out Shift RegisterGeneral Descriptionof the clock pulse through a two-input NOR gate, permittingThese parallel-in or ..
DM74LS166WM ,8-Bit Parallel-In/Serial-Out Shift RegisterDM74LS166 8-Bit Parallel-In/Serial-Out Shift RegisterAugust 1986Revised March 2000DM74LS1668-Bit Pa ..
DM74LS166WMX , 8-Bit Parallel-In/Serial-Out Shift RegisterGeneral Descriptionof the clock pulse through a two-input NOR gate, permittingThese parallel-in or ..
DM74LS169AN ,Synchronous 4-Bit Up/Down Binary Counterfeatures an internal counting up, and approximately equal to the low portion ofcarry look-ahead for ..
DM74LS170N ,4x4 REGISTER FILE WITH OPEN-COLLECTOR OUTPUTSFeatures
I Simultaneous read/write operation
I Expandable to 512 words of n-bits
I Typical ..
DM74LS170N ,4x4 REGISTER FILE WITH OPEN-COLLECTOR OUTPUTSElectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The 'meromm ..
DS2174Q+ ,EBERTAPPLICATIONS Software-programmable bit error insertion Routers Fully independent transmit and re ..
DS2174QN ,EBERTfeatures bit-serial, nibble-parallel, and byte-parallel data interfaces, and ngenerates and uniquel ..
DS2174QN+ ,EBERTPIN DESCRIPTION .82. PARALLEL CONTROL INTERFACE.......103. CONTROL REGISTERS ...113.1 MODE SELECT . ..
DS2175 ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2175S ,T1/CEPT Elastic StoreFEATURES PIN ASSIGNMENT• Rate buffer for T1 and CEPT transmissionsystems• Synchronizes loop–timed a ..
DS2176 ,T1 Receive BufferPIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION1 I Signaling Inhibit. When low, ABCD signaling u ..
DM74LS166N-DM74LS166WM
8-Bit Parallel-In/Serial-Out Shift Register
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register August 1986 Revised March 2000 DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register Clocking is accomplished on the LOW-to-HIGH level edge General Description of the clock pulse through a two-input NOR gate, permitting These parallel-in or serial-in, serial-out shift registers fea- one input to be used as a clock-enable or clock-inhibit func- ture gated clock inputs and an overriding clear input. All tion. Holding either of the clock inputs HIGH inhibits clock- inputs are buffered to lower the drive requirements to one ing; holding either LOW enables the other clock input. This normalized load, and input clamping diodes minimize allows the system clock to be free running, and the register switching transients to simplify system design. The load can be stopped on command with the other clock input. mode is established by the shift/load input. When HIGH, The clock-inhibit input should be changed to the high level this input enables the serial data input and couples the only while the clock input is HIGH. A buffered, direct clear eight flip-flops for serial shifting with each clock pulse. input overrides all other inputs, including the clock, and When LOW, the parallel (broadside) data inputs are sets all flip-flops to zero. enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Ordering Code: Order Number Package Number Package Description DM74LS166M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS166WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS166N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS006400
