DM74LS164MX , 8-Bit Serial In/Parallel Out Shift Register with Asynchronous ClearFeaturesThese 8-bit shift registers feature gated serial inputs and ■ Gated (enable/disable) serial ..
DM74LS164N ,8-Bit Serial In/Parallel Out Shift RegistersFeaturesYGated (enable/disable) serial inputsThese 8-bit shift registers feature gated serial input ..
DM74LS165M ,8-Bit Parallel In/Serial Output Shift RegistersDM74LS165 8-Bit Parallel In/Serial Output Shift RegistersAugust 1986Revised March 2000DM74LS1658-Bi ..
DM74LS165MX , 8-Bit Parallel In/Serial Out Shift RegisterFeaturesThis device is an 8-bit serial shift register which shifts data ■ Complementary outputsin t ..
DM74LS165N ,8-Bit Parallel In/Serial Output Shift RegistersFeaturesThis device is an 8-bit serial shift register which shifts data ■ Complementary outputsin t ..
DM74LS165N ,8-Bit Parallel In/Serial Output Shift Registers
DS2167Q , ADPCM Processor
DS2167Q , ADPCM Processor
DS2168 , ADPCM Processor
DS2172T ,Bit Error Rate Tester (BERT)applications requiring gap clocking such as Fractional-T1,Switched-56, DDS, normal framing requirem ..
DS2172T+ ,Bit Error Rate Tester (BERT)DS2172Bit Error Rate Tester (BERT)www.dalsemi.com
DS2172T+ ,Bit Error Rate Tester (BERT)applications requiring gap clocking such as Fractional-T1,Switched-56, DDS, normal framing requirem ..
DM74LS164MX
8-Bit Serial In/Parallel Out Shift Register with Asynchronous Clear
DM74LS164 8-Bit Serial In/Parallel Out Shift Register August 1986 Revised April 2000 DM74LS164 8-Bit Serial In/Parallel Out Shift Register General Description Features These 8-bit shift registers feature gated serial inputs and � Gated (enable/disable) serial inputs an asynchronous clear. A low logic level at either input � Fully buffered clock and serial inputs inhibits entry of the new data, and resets the first flip-flop to � Asynchronous clear the low level at the next clock pulse, thus providing com- � Typical clock frequency 36 MHz plete control over incoming data. A high logic level on either input enables the other input, which will then deter- � Typical power dissipation 80 mW mine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. Ordering Code: Order Number Package Number Package Description DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs Clear Clock A B Q Q ... Q A B H LX XX L L ... L HL XXQ Q ... Q A0 B0 H0 H ↑ H HHQ ... Q An Gn H ↑ LX L Q ... Q An Gn H ↑ XL L Q ... Q An Gn H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level Q , Q , Q = The level of Q , Q , or Q , respectively, before the A0 B0 H0 A B H indicated steady-state input conditions were established. Q , Q = The level of Q or Q before the most recent ↑ transition of the An Gn A G clock; indicates a one-bit shift. © 2000 DS006398
