DM74LS163AMX , Synchronous 4-Bit Binary Counter with Synchronous Clearapplications without addi-These synchronous, presettable counters feature an inter-tional gating. I ..
DM74LS163AN ,Synchronous 4-Bit Binary CountersFeaturesinput. The clear function for the LS161A is asynchronous;YSynchronously programmableand a l ..
DM74LS164M ,8-Bit Serial In/Parallel Out Shift RegistersFeaturesYGated (enable/disable) serial inputsThese 8-bit shift registers feature gated serial input ..
DM74LS164MX , 8-Bit Serial In/Parallel Out Shift Register with Asynchronous ClearFeaturesThese 8-bit shift registers feature gated serial inputs and ■ Gated (enable/disable) serial ..
DM74LS164N ,8-Bit Serial In/Parallel Out Shift RegistersFeaturesYGated (enable/disable) serial inputsThese 8-bit shift registers feature gated serial input ..
DM74LS165M ,8-Bit Parallel In/Serial Output Shift RegistersDM74LS165 8-Bit Parallel In/Serial Output Shift RegistersAugust 1986Revised March 2000DM74LS1658-Bi ..
DS21610SN+ ,3.3V/5V Clock Rate AdapterFEATURES The DS21610 is a multirate, low-jitter clock adapter Direct Replacement for LXP610SE tha ..
DS2164Q ,G.726 ADPCM Processorapplications Backward-compatible with the DS2165QADPCM processor chip Single +5V supply; low-powe ..
DS2165 ,16/24/32kbps ADPCM ProcessorDS2165Q16/24/32kbps ADPCM Processor
DS2165Q ,16/24/32kbps ADPCM ProcessorFEATURES PIN ASSIGNMENT (Top View) Compresses/expands 64kbps PCM voiceto/from either 32kbps, 24kbp ..
DS2165QN ,16/24/32kbps ADPCM ProcessorFEATURES PIN ASSIGNMENT (Top View) Compresses/expands 64kbps PCM voiceto/from either 32kbps, 24kbp ..
DS2165QN+ ,16/24/32kbps ADPCM Processorapplications Single +5V supply; low-power CMOStechnology Available in 28-pin PLCC 3V operation v ..
DM74LS163AMX
Synchronous 4-Bit Binary Counter with Synchronous Clear
DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters August 1986 Revised April 2000 DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters The carry look-ahead circuitry provides for cascading General Description counters for n-bit synchronous applications without addi- These synchronous, presettable counters feature an inter- tional gating. Instrumental in accomplishing this function nal carry look-ahead for application in high-speed counting are two count-enable inputs and a ripple carry output. designs. The DM74LS161A and DM74LS163A are 4-bit Both count-enable inputs (P and T) must be HIGH to count, binary counters. The carry output is decoded by means of and input T is fed forward to enable the ripple carry output. a NOR gate, thus preventing spikes during the normal The ripple carry output thus enabled will produce a high- counting mode of operation. Synchronous operation is pro- level output pulse with a duration approximately equal to vided by having all flip-flops clocked simultaneously so that the high-level portion of the Q output. This high-level over- A the outputs change coincident with each other when so flow ripple carry pulse can be used to enable successive instructed by the count-enable inputs and internal gating. cascaded stages. HIGH-to-LOW level transitions at the This mode of operation eliminates the output counting enable P or T inputs may occur, regardless of the logic spikes which are normally associated with asynchronous level of the clock. (ripple clock) counters. A buffered clock input triggers the These counters feature a fully independent clock circuit. four flip-flops on the rising (positive-going) edge of the clock input waveform. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking These counters are fully programmable; that is, the outputs occurs. The function of the counter (whether enabled, dis- may be preset to either level. As presetting is synchronous, abled, loading, or counting) will be dictated solely by the setting up a low level at the load input disables the counter conditions meeting the stable set-up and hold times. and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the DM74LS161A is asynchro- Features nous; and a low level at the clear input sets all four of the � Synchronously programmable flip-flop outputs LOW, regardless of the levels of clock, � Internal look-ahead for fast counting load, or enable inputs. The clear function for the � Carry output for n-bit cascading DM74LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the � Synchronous counting next clock pulse, regardless of the levels of the enable � Load control line inputs. This synchronous clear allows the count length to � Diode-clamped inputs be modified easily, as decoding the maximum count � Typical propagation time, clock to Q output 14 ns desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to � Typical clock frequency 32 MHz synchronously clear the counter to all low outputs. � Typical power dissipation 93 mW Ordering Code: Order Number Package Number Package Description DM74LS161AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS163AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS163AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 DS006397
