DM74LS126AMX , Quad 3-STATE BufferGeneral DescriptionThis device contains four independent gates each of whichperforms a non-invertin ..
DM74LS126AMX , Quad 3-STATE BufferDM74LS126A Quad 3-STATE BufferAugust 1986Revised March 2000DM74LS126AQuad 3-STATE Buffer
DM74LS126AN ,7 V, quad TRI-STATE bufferElectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recomm ..
DM74LS132M ,7 V, quad 2-input NAND gate with schmitt trigger inputElectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Ratpom ..
DM74LS132N ,7 V, quad 2-input NAND gate with schmitt trigger inputNational
Semiconductor
DM54LS132/DM74LS132 Quad 2-lnput
NAND Gates with Schmitt Trigger Inputs ..
DM74LS132SJ ,Quad 2-Input NAND Gate with Schmitt Trigger InputGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND ..
DS21455+ ,Quad T1/E1/J1 TransceiversTABLE OF CONTENTS 1. DESCRIPTION ........ 9 1.1 STANDARDS . 10 2. FEATURE HIGHLIGHTS 11 2.1 GENERAL ..
DS21458 ,Quad T1/E1/J1 TransceiversApplications Interleaving PCM Bus Operation 256 BGA DS21455 0°C to +70°C (27mm x 27mm) 8-Bit Pa ..
DS21458N+ ,Quad T1/E1/J1 TransceiversAPPLICATIONS Detector Routers Internal Software-Selectable Receive- and Channel Service Units (CS ..
DS21458N+ ,Quad T1/E1/J1 TransceiversApplications (27mm x 27mm) Interleaving PCM Bus Operation 256 BGA DS21455+ 0°C to +70°C (27mm x 2 ..
DS21458N+ ,Quad T1/E1/J1 TransceiversBLOCK DIAGRAM 15 4. DS21455/DS21458 DELTA..... 17 4.1 PACKAGE..... 17 4.2 CONTROLLER INTERFACE 17 ..
DS2148 ,5V E1/T1/J1 Line InterfaceFEATURES Complete E1, T1, or J1 Line Interface Unit TOP VIEW 44(LIU) Supports Both Long- and ..
DM74LS126AMX
Quad 3-STATE Buffer
DM74LS126A Quad 3-STATE Buffer August 1986 Revised March 2000 DM74LS126A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-imped- ance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possi- bility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order Number Package Number Package Description DM74LS126AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS126AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = A Inputs Output AC Y LH L HH H X L Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) © 2000 DS006388
