DM74LS125AMX , Quad 3-STATE BufferGeneral DescriptionThis device contains four independent gates each of whichperforms a non-invertin ..
DM74LS125AN ,Quad 3-STATE BufferNational
Semiconductor
64LtM25A/DM54LS12tiA/DM74LtM25A
Quad TRI-STATE® Buffers
DM74LS125ASJ ,Quad 3-STATE BufferGeneral DescriptionThis device contains four independent gates each of whichperforms a non-invertin ..
DM74LS125ASJ ,Quad 3-STATE BufferDM74LS125A Quad 3-STATE BufferAugust 1986Revised March 2000DM74LS125AQuad 3-STATE Buffer
DM74LS126AM ,7 V, quad TRI-STATE bufferGeneral Description
This device contains four independent gates each of which
performs a non-in ..
DM74LS126AM ,7 V, quad TRI-STATE bufferL6126A
National
Semiconductor
54LS126/DM74LS126A Quad TRI-STATE® Buffers
DS2143QN+ ,E1 ControllerapplicationsAD4 10 31 LI_CS Onboard Sa data link support circuitryAD5 LI_CLK11 3012 29 FEBE E-Bit ..
DS21448 ,3.3V E1/T1/J1 Quad Line InterfaceAPPLICATIONS CSU Line Build-Outs for T1 Integrated Multiservice Access Platforms AMI, HDB3, and B ..
DS21448DK ,3.3V E1/T1/J1 Line Interface Design Kit Daughter CardFEATURES The DS21448DK is an easy-to-use evaluation board Demonstrates Key Functions of the DS214 ..
DS21448L ,3.3V E1/T1/J1 Quad Line Interfaceapplications). Intel or Motorola Detects/Generates Blue (AIS) Alarms The DS21448 has diagnostic ..
DS21448L+ ,3.3V E1/T1/J1 Quad Line InterfacePIN DESCRIPTION .....7 3. DETAILED DESCRIPTION 13 3.1 DS21448 AND DS21Q348 DIFFERENCES.....13 4. PO ..
DS21448L+W ,3.3V E1/T1/J1 Quad Line InterfaceAPPLICATIONS CSU Line Build-Outs for T1 Integrated Multiservice Access Platforms AMI, HDB3, and B ..
DM74LS125AMX
Quad 3-STATE Buffer
DM74LS125A Quad 3-STATE Buffer August 1986 Revised March 2000 DM74LS125A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-imped- ance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possi- bility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order Number Package Number Package Description DM74LS125AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS125ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS125AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = A Inputs Output AC Y LLL HL H X H Hi-Z H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) © 2000 DS006387
