DM74LS107AN ,Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary OutputsDM54LS107A/DM74LS107ADualNegative-Edge-TriggeredMaster-SlaveJ-KFlip-FlopswithClearandComplementaryO ..
DM74LS109AM ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered J-K flip-flops wit ..
DM74LS109AMX , Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsDM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs ..
DM74LS109AMX , Dual Positive Edge-Triggered J-K Flip-Flop with Preset Clear and Complementary OutputsGeneral DescriptionThis device contains two independent positive-edge-trig-gered J-K flip-flops wit ..
DM74LS109AN ,Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary OutputsFeaturesnotdirectlyrelatedtothetransitiontimeoftherisingedgeofYAlternate Military/Aerospace device ..
DM74LS10M ,Triple 3-Input NAND GatesGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic NAN ..
DS21349DK ,T1/J1 Line Interface Unit Design Kit DS2149DK/DS21349DK T1/J1 Line Interface Unit Design Kit
DS21349Q ,3.3V T1/J1 Line Interface UnitTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......4 2. OPERATING MODES......5 3. INITIALIZATION AND R ..
DS21349Q+ ,3.3V T1/J1 Line Interface UnitAPPLICATIONS Four CSU Filters from 0dB to -22.5dB Routers Transmit/Receive Performance Monitors ..
DS21352 ,3.3V DS21352 and 5V DS21552 T1 Single Chip TransceiversFUNCTIONAL DESCRIPTION....83.2 DOCUMENT REVISION HISTORY...104.
DS21352DK ,T1 Single-Chip Transceiver Design Kit Daughter CardFEATURES The DS21352 design kit is an easy-to-use evaluation Demonstrates Key Functions of DS2135 ..
DS21352G ,3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers3.3V DS21352 and 5V DS21552T1 Single-Chip Transceivers
DM74LS107AN
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
TL/F/6367
DM54LS107A/DM74LS107A
Dual
Negative-Edge-Triggered
Master-Slave
J-K
Flip-Flops
with
Clear
and
Complementary
Outputs
June 1989
DM54LS107A/DM74LS107A Dual Negative-Edge-
Triggered Master-Slave J-K Flip-Flops with
Clear and Complementary Outputs
General Description
This device containstwo independent negative-edge-trig-
geredJ-K flip-flops with complementary outputs. TheJand datais processedbythe flip-flopsonthe falling edgeof
the clock pulse. The clock triggering occursata voltage
levelandisnot directly relatedtothe transition timeofthe
negative going edgeofthe clock pulse.The dataontheJ
andK inputs may change whilethe clockis highorlow
without affectingthe outputsas longas setup and hold
timesarenot violated.Alow logic levelonthe clear input
will resetthe outputs regardlessofthe logic levelsofthe
other inputs.
Connection Diagram
Dual-In-Line Package
TL/F/6367–1
Order NumberDM54LS107AJ, DM54LS107AW, DM74LS107AMor DM74LS107AN
SeeNS Package Number J14A,M14A, N14Aor W14B
Function Table
Inputs Outputs
CLR CLK J K Q Q X X L H v LL Q0 Q0 v HL H L v LH L H v H H Toggle X X Q0 Q0eHigh Logic Levele EitherLow orHighLogicLeveleLow Logic Levele Negative goingedgeof pulse.eThe outputlogiclevel beforethe indicatedinput conditionswere established.
ToggleeEach outputchangestothe complementofits previousleveloneach fallingedgeofthe clock pulse.
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
