DM74LS05N ,Hex Inverters with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM74LS05SJ ,Hex Inverters with Open-Collector OutputsDM74LS05 Hex Inverters with Open-Collector OutputsAugust 1986Revised March 2000DM74LS05Hex Inverter ..
DM74LS05SJ ,Hex Inverters with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains six independent gates each of wh ..
DM74LS08 ,Quad 2-Input AND GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic AND ..
DM74LS08M ,Quad 2-Input AND GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic AND ..
DM74LS08N ,Quad 2-Input AND GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic AND ..
DS2125 ,Ultra3 LVD/SE 15-Line SCSI TerminatorAPPLICATIONS HS_GND HS_GNDHS_GND HS_GNDHS_GND HS_GNDRaid Systems VREF TPWRR1P R15NSCSI Host Bus Ad ..
DS2125-C01/T&R ,Ultra3 LVD/SE 15-Line SCSI TerminatorAPPLICATIONS HS_GND HS_GNDHS_GND HS_GNDHS_GND HS_GNDRaid Systems VREF TPWRR1P R15NSCSI Host Bus Ad ..
DS21348G ,3.3V E1/T1/J1 line interfaceTABLE OF CONTENTS1. LIST OF FIGURES. 42. LIST OF TABLES .. 53. INTRODUCTION... 63.1 DOCUMENT REVISI ..
DS21348G+ ,3.3V E1/T1/J1 Line Interfaceapplications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity ..
DS21348GN ,3.3V E1/T1/J1 line interfaceapplications.Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity a ..
DS21348GN+ ,3.3V E1/T1/J1 Line Interfaceapplications. The crystal-less on-board jitter attenuator requires only a 2.048MHz MCLK for both E1 ..
DM74LS05M-DM74LS05N-DM74LS05SJ
Hex Inverters with Open-Collector Outputs
DM74LS05 Hex Inverters with Open-Collector Outputs August 1986 Revised March 2000 DM74LS05 Hex Inverters with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation. Where: N (I ) = total maximum output high current 1 OH for all outputs tied to pull-up resistor N (I ) = total maximum input high current for 2 IH all inputs tied to pull-up resistor N (I ) = total maximum input low current for 3 IL all inputs tied to pull-up resistor Ordering Code: Order Number Package Number Package Description DM74LS05M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS05SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS05N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = A Input Output AY LH HL H = HIGH Logic Level L = LOW Logic Level © 2000 DS006346
