DM74AS74MX ,Dual D Positive-Edge-Triggered Flip-Flop with Preset and ClearFeaturesThe AS74 is a dual edge-triggered flip-flops. Each flip-flop ■ Switching specifications at ..
DM74AS74N ,Dual D Positive-Edge-Triggered Flip-Flop with Preset and ClearFeaturesThe AS74 is a dual edge-triggered flip-flops. Each flip-flop ■ Switching specifications at ..
DM74AS804BN ,Hex 2 Input NAND DriverDM74AS804B Hex 2-Input NAND DriverOctober 1986Revised April 2000DM74AS804BHex 2-Input NAND Driver
DM74AS804BN ,Hex 2 Input NAND DriverFeaturesThese devices contain six independent drivers, each of
DM74AS74M-DM74AS74MX-DM74AS74N
Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear April 1984 Revised March 2000 DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The AS74 is a dual edge-triggered flip-flops. Each flip-flop � Switching specifications at 50 pF has individual D, clock, clear and preset inputs, and also � Switching specifications guaranteed over full tempera- complementary Q and Q outputs. ture and V range CC Information at input D is transferred to the Q output on the � Advanced oxide-isolated, ion-implanted Schottky TTL positive going edge of the clock pulse. Clock triggering process occurs at a voltage level of the clock pulse and is not � Functionally and pin-for-pin compatible with Schottky directly related to the transition time of the positive going and LS TTL counterpart pulse. When the clock input is at either the HIGH or LOW � Improved AC performance over S74 at approximately level, the D input signal has no effect. half the power Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of LOW level sig- nal. Ordering Code: Order Number Package Number Package Description DM74AS74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS74SJX M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74AS74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D Q Q LH X X H L HL X X L H L L X X H (Note 1) H (Note 1) HH ↑ HH L HH ↑ LL H HH L X Q Q 0 0 L = LOW State H = HIGH State X = Don't Care ↑ = Positive Edge Transition Q = Previous Condition of Q 0 Note 1: This condition is nonstable; it will not persist when preset and clear inputs return to their inactive (HIGH) level. The output levels in this condi- tion are not guaranteed to meet the V specification. OH © 2000 DS006282
