DM74AS648NT ,Octal 3-STATE Inverting Bus Transceiver RegisterFeaturesThis device incorporates an octal bus transceiver and an
DM74AS646NT-DM74AS646WM-DM74AS648NT
Octal 3-STATE Bus Transceiver Register
DM74AS646 • DM74AS648 Octal Bus Transceiver and Register October 1986 Revised July 2003 DM74AS646 DM74AS648 Octal Bus Transceiver and Register General Description Features This device incorporates an octal bus transceiver and anSwitching specifications at 50 pF octal D-type register configured to enable multiplexedSwitching specifications guaranteed over full tempera- transmission of data from bus to bus or internal register to ture and V range CC bus. Advanced oxide-isolated, ion-implanted Schottky TTL This bus transceiver features totem-pole 3-STATE outputs process designed specifically for driving highly-capacitive or rela- Functionally and pin-for-pin compatible with LS TTL tively low-impedance loads. The high-impedance third counterpart state and increased high-logic-level drive provide this 3-STATE buffer-type outputs drive bus lines directly device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidi- rectional bus drivers, and working registers. The registers in the DM74AS646, DM74AS648 are edge- triggered D-type flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would nor- mally occur in a typical multiplexer during the transition between stored and real-time data. The enable G and direction control pins provide four modes of operation; real-time data transfer from bus A to B, real- time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. Ordering Code: Order Number Package Number Package Description DM74AS646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74AS646NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide DM74AS648WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide DM74AS648NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 DS006324
