DM74AS640N ,Octal 3-STATE Octal Bus TransceiverFeaturesThis advanced Schottky device contains 8 pairs of 3- ■ Switching specifications at 50 pFSTA ..
DM74AS646NT ,Octal 3-STATE Bus Transceiver RegisterFeaturesThis device incorporates an octal bus transceiver and an
DM74AS640N
Octal 3-STATE Octal Bus Transceiver
DM74AS640 3-STATE Octal Bus Transceiver October 1986 Revised March 2000 DM74AS640 3-STATE Octal Bus Transceiver General Description Features This advanced Schottky device contains 8 pairs of 3- � Switching specifications at 50 pF STATE logic elements configured as octal bus transceiver. � Switching specifications guaranteed over full tempera- This circuit is designed for use in memory, microprocessor ture and V range CC systems and in asynchronous bidirectional data buses. � Advanced oxide-isolated, ion-implanted Schottky TTL This device transmits data from the A bus to the B bus, or process vice versa, depending upon the logic level of the direction � Functionally and pin for pin compatible with Schottky, control input (DIR). The enable input (G) can be used to low power Schottky, and advanced low power Schottky disable the devices, effecting isolation of buses A and B. TTL counterpart The 3-STATE circuitry also contains a protection feature � Improved AC performance over Schottky, low power that prevents these transceivers from glitching the bus dur- Schottky, and advanced low power Schottky counter- ing power-up or power-down. parts � 3-STATE outputs independently controlled on A and B buses � Low output impedance drive to drive terminated trans- mission lines to 133Ω � Specified to interface with CMOS at V = V − 2V OH CC Ordering Code: Order Number Package Number Package Description DM74AS640WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74AS640N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Control Inputs Operation G DIR LL B Data to A Bus LH A Data to B Bus HX Isolation H = HIGH Logic Level L = LOW Logic Level X = Immaterial Logic Diagram Top View © 2000 DS006708
